Link_Capability_2 - 0Xd8; Link_Status_Control_2 - 0Xdc - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
CMPL_TIMEOUT_DISABLE
CMPL_TIMEOUT_VALUE
LINK_CAPABILITY_2 – 0xd8
Name
LINK_CAPABILITY_2
LINK_STATUS_CONTROL_2 – 0xdc
This register will be Read only by default, and will read all 0's to allow compliance with PCIE spec 1.1. To enable
this register, reset comply_pcie_1_1 bit in the register space to 0.
Name
LINK_STATUS_2
CURR_DEEMPH_LEVEL
Unused0
CFG_COMPLIANCE_DEEM
PH
CFG_COMPLIANCE_SOS
CFG_ENTER_MOD_
COMPLIANCE
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
4 RW 0
3:0 RW 0
Default
Bits Access Value
31:0 RO 0
Default
Bits Access Value
31:17 RO 0
16 RO 0
15:13 RO 0
12 RW 0
11 RW 0
10 RW 0
Description
Completion Timeout Disable
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Value Name
0 50MS
1 100US
2 10MS
3 55MS
4 210MS
5 900MS
6 3_5S
13S
8 64S
255 –
Description
Placeholder for Gen2 Path=
i_cfg_func.i_cfg_private
Description
Placeholder for Gen2
curr_deemph_level Path = pl_top
–
Compliance De-emphasis.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Compliance SOS.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Enter Modified Compliance.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
PCI Configuration Registers
Description
50ms
100us
10ms
55ms
210ms
900ms
3.5s
13s
64s
end_of_table
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