BCM5718 Programmer's Guide
Bit
Name
6:4
DELAY VALUE
3:0
DELAY LINE SELECTOR RW
1Ch: Spare Control 2 Register (Shadow Register Selector = "04h")
Bit
Name
15
WRITE ENABLE
14:10 SHADOW REGISTER
SELECTOR
9
SPARE
8
wirespeed retry disable
(fixed in 54980)
7
select tpout_rxd
6
DISABLE PHYA2
5
enable rbc0/1 & txc/rxc tri
sate
Broadcom
®
January 29, 2016 • 5718-PG108-R
RW
Description
RW
RXCLK delay: reset = default delay
000 = +1 unit delay
...
111 = +8 units delay
GMII clock delay:
110 = –1.0ns
111 = –0.5ns
000 = 0ns
001 = 0.5ns
010 = 1.0ns
RXCLK strobe:
xx00 = std cell rxclk
xx01 = dfse rxclk
xx10 = dfe rxclk
xx11 = enc rxclk
GMII clock strobe:
0111 = TBI gtx_clk
1000 = GMII gtx_clk
1001 = RGMII gtx_clk
1010 = GMII rx_clk
1011 = RGMII rx_clk
1100 = TBI RBC0
1101 = TBI RBC1
RW
Description
RW
1 = write bits [9:0]
0 = read bits [9:0]
RW
Shadow Register Selector
RW
Flop exists, but does not change any function. 0
RW
1 = downgrade after 1 failed link attempt
0 = use wirespeed retry limit (1c-04.4:2)
RW
1 = tpout_rxd port muxed to rxd
0 = normal operation for rxd
RW
1 = internally disable phya2 input (consult
Testability document for suggested usage).
RW
1 = enable tristating of rbc0/1 or txc/rxc
0 = rbc0/1 & txc/rxc not tristated.
10h–1Fh Register Map Detailed Description
Default
000
0000
Default
0
00100
0
0
0
0
Page 526
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