Msi Lower Address Register (Offset: 0X5C); Msi Upper Address Register (Offset: 0X60); Msi Data Register (Offset: 0X64); Miscellaneous Host Control Register (Offset: 0X68) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

MSI Lower Address Register (offset: 0x5C)

Name Bits
MSI Lower 31:2
Address
Reserved 1:0

MSI Upper Address Register (offset: 0x60)

Name Bits
MSI Upper 31:0
Address

MSI Data Register (offset: 0x64)

Name Bits
MSI Data 15:0

Miscellaneous Host Control Register (offset: 0x68)

Name
ASIC Rev ID
Enable TLP Minor Error
Tolerance
Log Header Overflow
Boundary check
Byte enable Rule Check
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Access Value
RW Unknown MSI Lower Address
RO 0
Default
Access Value Description
RW Unknown MSI Upper Address
Default
Access Value Description
RW Unknown MSI Data
Default
Bits Access Value
31:28 R Product ID
input
27:24 R ASIC Rev
Input
23:16 R ASIC Rev
Input
15 RW 0
14 RW 0
13 RW 0
12 RW 0
Description
–
Description
0xF: Indication that BCM5718 family follows new
PRODUCT/REV ID mapping
External All Layer Revision ID.
These bits will reflect in offset 8-bit mapping
description:
0x0: A
0x1: B
0x2: C
Metal Rev Number
0x0: 0
0x1: 1
0x2: 2
Set this bit to enable TLP minor error tolerance
(ATTR/TC/LOCK command)
Set this bit to enable log header due to overflow
Set this bit to enable crossing 4 KB boundary
check
Set this bit to enable the byte enable rule check
PCI Configuration Registers
Page 282