Host Address For The Dma Read Channel 3 (Offset: 0X4B40); Non-Lso Read Dma Reserved Control Register (Offset: 0X4B74); Non-Lso Read Dma Flow Reserved Control Register (Offset: 0X4B78) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Host Address for the DMA Read Channel 3 (offset: 0x4B40)

Name
Host Addr

Non-LSO Read DMA Reserved Control Register (offset: 0x4B74)

Name
Txmbuf_margin
Reserved
FIFO High Mark
FIFO Low Mark
Slow Clock Fix Disable
Hardware fix enable for DMA
FIFO Overrun
Late Collision Fix Enable
Select FED Enable

Non-LSO Read DMA Flow Reserved Control Register (offset: 0x4B78)

Name
Fix for frequent TX time out.
Fifo_threshold_mbuf_req
MBUF Threshold MBUF
Request
Reserved
Clock Request Fix Enable
MBUF Threshold Clk Req
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:0 RO 0
Default
Bits Access Value
31:21 RO 0
20 RO 0
19:12 RO 0x90
11:4 RO 0x40
3 RO 0
2 RO 0
1 RO 0
0 RO 0
Default
Bits Access Value
31:24 RW 0
23:16 RO 0x30
15:8 RO 0x54
7 RO 0
6 RO 0
5:0 RO 0x7
Description
Latched host address
Description
–
–
–
–
When cleared, it enables the fix to cover a corner
case in the link idle mode to allow the DMA Read
request to be generated when the core clock is
transitioning from slow to fast.
When set, this bit enables the fix for DMA FIFO
overrun occurs if a large number of Rx BDs are
fetched while the Tx MBUF is full and the Read
DMA FIFO is empty.
0: Disable Fix
1: Enable Fix
Ensure only 1 request is generated upon any
condition where the core clock is switching from
slow to fast or vice-versa.
Description
This register contains various controls to
configure hardware fix for the chip getting stuck
in a permanent XOFF state under heavy
bi-directional netperf traffic when flow control is
enabled.
–
–
–
–
–
RDMA Registers
Page 447