Msi-X Capabilities Registers; Msi-X Capability Header Register (Offset: 0Xa0); Msix_Tbl_Off_Bir - 0Xa4; Msix_Pba_Bir_Off - 0Xa8 - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

MSI-X Capabilities Registers

MSI-X Capability Header Register (offset: 0xA0)

Name
MSIX_ENABLE
FUNC_MASK
RESERVED
TABLE_SIZE
MSIX_NEXT_CAP_PTR
MSIX_CAP_ID
MSIX_TBL_OFF_BIR – 0xa4
Name
TABLE_OFFSET
TABLE_BIR
MSIX_PBA_BIR_OFF – 0xa8
Name
TABLE_OFFSET
TABLE_BIR
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31 RW 0
30 RW 0
29:27 RO 0
26:16 RO 0
15:8 RO 0xac
7:0 RO 0x11
Default
Bits Access Value
31:3 RO 0
2:0 RO 0
Default
Bits Access Value
31:3 RO 0
2:0 RO 0
Description
If 1 and the MSI enable bit in the MSI message
control register is 0, the function is permitted to
use MSIX request service and profited from using
INTx# messages.
Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
If 1, all of the vectors associated with the function
are masked regardless of their per vector Mask
bit.
Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
Reserved
System sw reads this field to determine the MSI-X
table size N, which is encoded as N-1
Path = i_cfg_func.i_cfg_private
This value continues the PCI capability chain. It's
value specified as offset in the PCI address space
of the next capability. The read-only value of this
register is controlled by the CAP_ENA register in
the PCI register space.
Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
Capability ID for MSIX Path = cfg_defs
Description
Path = i_cfg_func.i_cfg_private
Indicates which one of functions BAR is used to
map MSI-X table into memory space.
Path = i_cfg_func.i_cfg_private
Description
Path = i_cfg_func.i_cfg_private
Indicates which one of functions BAR is used to
map MSI-X table into memory space.
Path = i_cfg_func.i_cfg_private
PCI Configuration Registers
Page 288