Rx Risc Status Register (Offset: 0X5004) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Enable Write Post Buffers
Enable Page 0 Instr Halt
Enable Page 0 Data Halt
Single-Step RX RISC
Reset RX RISC

RX RISC Status Register (offset: 0x5004)

The RX RISC State register reports the current state of the RX RISC and, if halted, gives reasons for the halt.
There are four categories of information; informational (read-only), informational (write-to-clear), disable-able
halt conditions (write-to-clear), and non-disable-able halt conditions (write-to-clear).
Name
Blocking Read
MA Request FIFO overflow
MA data/bytemask FIFO
overflow
MA outstanding read FIFO
overflow
MA outstanding write FIFO
overflow
Reserved
Instruction fetch stall
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
4 RW 0
3 RW 0
2 RW 0
1 RW 0
0 WO 0
Default
Bits Access Value
31 RO 0
30 W2C 0
29 W2C 0
28 W2C 0
27 W2C 0
26:16 RO 0
15 RO 0
Description
Enables absorption of multiple software
operations for SRAM and register writes. When
this bit is disabled, only one write at a time will be
absorbed by the write post buffers. Cleared on
reset.
Note: Setting this bit on the BCM5705,
BCM5721, and BCM5751 may cause
unpredictable behavior.
When set, instruction references to the first 256
bytes of SRAM force the RX RISC to halt and
cause bit 4 in the RX RISC state register to be
latched. Cleared on reset and Watchdog
interrupt.
When set, data references to the first 256 bytes
of SRAM force the RX RISC to halt and cause bit
3 in the RX RISC state register to be latched.
Cleared on reset and Watchdog interrupt.
Advances the RX RISC's PC for one cycle. If
halting condition still exists, the RX RISC will
again halt; otherwise, it will resume normal
operation.
Self-clearing bit which resets only the RX RISC.
Description
A blocking data cache miss occurred, causing
the RX RISC to stall while data is fetched from
external (to the RX RISC) memory. This is
intended as a debugging tool. No state is saved
other than the fact that the miss occurred.
MA_req_FIFO overflowed. The RX RISC is
halted on this condition.
MA_datamask_FIFO overflowed. The RX RISC
is halted on this condition.
MA_rd_FIFO overflowed. The RX RISC is halted
on this condition.
MA_wr_FIFO overflowed. The RX RISC is halted
on this condition.
–
The processor is currently stalled due to an
instruction fetch.
RX-CPU Registers
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