Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 293

BCM5718 Programmer's Guide
Name
L1_EXIT_LAT
L0S_EXIT_LAT
ASPM_SUPT
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
17:15 RO 0x2
14:12 RO 0x5
11:10 RO 0x3
Description
L1 Exit Latency. These bits are programmable
through register space.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Depending on whether device is in common clock
mode or not, the value reflected by these bits is
one of the following.
Value Name Description
1 1_2 L1 exit latency of 1 us to 2 us.
2 2_4 L1 exit latency of 2 us to 4 us.
255 – end_of_table
L0s Exit Latency. These bits are programmable
through register space.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Depending on whether device is in common clock
mode or not, the value reflected by these bits is
one of the following.
Value Name
4 0_1
5 1_2
255 –
ASPM Support. These bits are programmable
through reg space.
Path= i_cfg_func.i_cfg_private
Value Name
0 RES_0
1 L0S
2 RES_2
3 L0S_L1
255 –
Path= i_cfg_func.i_cfg_private Value used by
internal logic is the smaller of the value
programmed for each function
PCI Configuration Registers
Description
L0s exit latency of 512
ns to 1 us.
L0s exit latency of 1 us
to 2 us.
end_of_table
Description
Reserved
L0s entry supported
Reserved
L0s and L1 supported
end_of_table
Page 293