Message Signaled Interrupt Registers; Msi Mode Register (Offset: 0X6000) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Reserved
Valid Bit
Skip Bit
Pass Bit
Head RXMBUF Pointer
Tail RXMBUF Pointer

Message Signaled Interrupt Registers

All registers reset are core reset unless specified.

MSI Mode Register (offset: 0x6000)

Name
Priority
(BCM5718) Reserved
(BCM5719) Reserved
(BCM5719) MSI ST Lower
(BCM5719) Reserved
MSI Message
(BCM5718) Reserved
(BCM5719) MSIX Multimode
Vector Enable
MSI Byte Swap
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:21 RO 0
20 RW 0
19 RW 0
18 RW 0
17:9 RO 0
8:0 RO 0
Default
Bits Access Value
31:30 RW 0
29:11 RO 0
29:24 RO 0
23:16 RW 0x01
15;11 RO 0
10:8 RW 0
7 RO 0
7 RW 0
6 0
Message Signaled Interrupt Registers
Description
–
Set only if the head of RDIQ entry is valid.
If this bit is set, the head of RDIQ entry will be
popped.
This bit is 0 if RDIQ head entry is intended for the
CPU. It prevents the entry to be serviced by
WDMA.
Specifies the first MBUF of the RXMBUF cluster
for the received packet.
Specifies the last MBUF of the RXMBUF cluster
for the received packet.
Description
Sets the priority of the MSI engine relative to the
DMA read engine and DMA Write engine. Equal
settings result in fair round robin arbitration.
• 00: Lowest
• 01: Low
• 10: High
• 11: Highest
–
–
This 8-bit value is used as the TPH Steering Tag
when both TPH Interrupt Vector mode and MSI
mode are enabled.
–
This register sets the MSI message data bottom
bits to the value programmed here. This register
exists only for testing purposes and should
always be programmed to zero.
–
–
–
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