Mem Tm Control 3(Offset: 0X68E8); Expansion Rom Address Register (Offset: 0X68Ec); Bcm5719/Bcm5720 Registers; Mem Tm Control 4 (Offset: 0X68F8) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Mem TM control 3(offset: 0x68E8)

Name
Reserved
Memory TM control boot rom
Memory TM control scratchpad 3:0

Expansion ROM Address Register (offset: 0x68EC)

Name
Expansion ROM Test bits
Expansion ROM base address 23:0

BCM5719/BCM5720 Registers

The registers in this section are available only for the BCM5719 and BCM5720.

Mem TM Control 4 (offset: 0x68F8)

Name
Reserved
WDMA FIFO tmb
control
WDMA FIFO tma
control
Non-LSO Ch3 RDMA
FIFO tmb control
Non-LSO Ch3 RDMA
FIFO tma control
Non-LSO Ch2 RDMA
FIFO tmb control
Non-LSO Ch2 RDMA
FIFO tma control
Non-LSO Ch1 RDMA
FIFO tmb control
Non-LSO Ch1 RDMA
FIFO tma control
Non-LSO Ch0 RDMA
FIFO tmb control
Broadcom
®
January 29, 2016 • 5718-PG108-R
Bits Access
31:9 RW
8:4 RW
RW
Bits Access
31:24 RW
RW
Default
Bits Access Value
31:28 RW 0x0
27:26 RW 0x00
25:24 RW 0x00
23:22 RW 0x00
21:20 RW 0x00
19:18 RW 0x00
17:16 RW 0x00
15:14 RW 0x00
13:12 RW 0x00
11:10 RW 0x00
Default
Value Description
0x0 –
0x00 TM control for rom
0x00 TM control for scratchpad
Default
Value Description
0 Reserved–keep at 0 for normal operation.
0 Expansion ROM base address, expect to be d-
word aligned.
Description
Reserved
TM control for WDMA engine memory.
TM control for WDMA engine memory.
TM control for Ch3 non-LSO RDMA engine memory.
TM control for Ch3 non-LSO RDMA engine memory.
TM control for Ch2 non-LSO RDMA engine memory.
TM control for Ch2 non-LSO RDMA engine memory.
TM control for Ch1 non-LSO RDMA engine memory.
TM control for Ch1 non-LSO RDMA engine memory.
TM control for Ch0 non-LSO RDMA engine memory.
Miscellaneous Control Registers
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