Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 469

BCM5718 Programmer's Guide
Name
Interrupt on RX RISC Attention 25
TXCP_ATTN_INT_EN
Receive No Pseudo-header
checksum
Pcie TL/DL/PL mapping bit
NVRAM Write Enable
Send No Pseudo-header
checksum
Time Sync Mode Enable
HTX2B Feature Enable
(BCM5720)
Host Send BDs
Host Stack Up
B2HRX Feature Enable
Don't Interrupt on Receives
Don't Interrupt on Sends
DW_SYS_ATTN
Allow Bad Frames
NO_CRC
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
RW 0
24 RO 0
23 RW 0
22 RO 0
21 RW 0
20 RW 0
19 RW 0
18 RW 0
17 RW 0
16 RW 0
15 RW 0
14 RW 0
13 RW 0
12 RO 0
11 RW 0
10 RO 0
Description
Cause a host interrupt when an enabled RX-
RISC attention occurs.
TXCP attention bit.
Do not include the pseudo-header in the TCP or
UDP checksum calculations. To obtain the
correct checksum, the driver must add the TCP/
UDP checksum field to the pseudo-header
checksum.
–
The host must set this bit before attempting to
update the Flash or SEEPROM
Note: This bit is only valid when set from GRC
port 0. Setting/clearing of this bit from GRC port
1 does not affect NVRAM write access control.
For BCM5718 family, it is recommended to use
0x7024[1] from all ports to control NVRAM write
access.
Do not include the pseudo-header in the TCP or
UDP checksum calculations. To obtain the
correct checksum, the driver must seed the TCP/
UDP checksum field with the pseudo-header
checksum.
Write 1 to this bit to enable Time Sync Mode.
Write 1 to enable TX-MAC to route HTX2B
packets to the APE. Firmware may enable/
disable this in flight with careful coordination.
Use host-based BD rings instead of NIC-based
BD rings.
The host stack is ready to receive data from the
NIC.
Write 1 to enable DMA Engine to route B2HRX
packets to PCIe. Firmware may enable/disable
this in flight with careful coordination.
Never cause an interrupt on receive return ring
producer updates.
Never cause an interrupt on send BD ring
producer updates.
WDMA attention bit.
The RX MAC forwards illegal frames to the NIC
and marks them as such instead of discarding
them. The frames are queued based on default
class and interrupt distribution queue number.
–
GRC Registers
Page 469