Other Configuration Controls; Broadcom Mask Mode; Broadcom Tagged Status Mode; Clear Ticks On Bd Events Mode - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Other Configuration Controls

Other Configuration Controls

Broadcom Mask Mode

Enabled by setting the Mask_Interrupt_Mode bit (bit 8) of the Miscellaneous Host Control register (see
"Miscellaneous Host Control Register (offset: 0x68)" on page 282). When enabled, setting the mask bit of the
Miscellaneous Host Control register will mask (deassert) the INTA signal at the pin, but it will not clear the
interrupt state and it will not latch the INTA value. Clearing the mask bit will enable the interrupt state to
propagate to the INTA signal. Note that the During Interrupt Coalescence registers are only used when the
Mailbox 0 is set.

Broadcom Tagged Status Mode

Enabled by setting the Status Tagged Status mode bit of the Miscellaneous Host Control register (see
"Miscellaneous Host Control Register (offset: 0x68)" on page 282). When enabled, a unique eight-bit tag value
will be inserted into the Status Block Status Tag at location 7:0. The Status Tag can be returned to the Mailbox
0 register at location 31:24 by the host driver. When the Mailbox 0 register field 23:0 is written with a zero value,
the tag field of the Mailbox 0 register is compared with the tag field of the last Status Block to be DMAed to the
host. If the tag returned is not equivalent to the tag of the first Status Block DMAed, the interrupt status is
entered.

Clear Ticks on BD Events Mode

Enabled by setting the Clear Ticks mode on RX or the Clear Ticks mode on TX bits of the Host Coalescing Mode
register (see "Miscellaneous Host Control Register (offset: 0x68)" on page 282). When enabled, the counters
initialize to the idle state and begin counting only after a receive or transmit BD event is detected.

No Interrupt on Force Update

Enabled by setting the No Interrupt on Force bit of the Host Coalescing Mode register (see "Host Coalescing
Mode Register (offset: 0x3C00)" on page 413). When enabled, writing the Force update bit of the Host
Coalescing Mode register will cause a status block update without a corresponding interrupt event.

No Interrupt on DMAD Force

Enabled by setting the No Interrupt on DMAD force bit of the Host Coalescing Mode register (see "Host
Coalescing Mode Register (offset: 0x3C00)" on page 413). When enabled, the BD_FLAG_COAL_NOW bit of
the buffer descriptor may be set to force a status block update without a corresponding interrupt.
Broadcom
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January 29, 2016 • 5718-PG108-R Page 262