Pci Configuration Registers; Device Id And Vendor Id Register (Offset: 0X00); Status And Command Register (Offset: 0X04) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

PCI Configuration Registers

Device ID and Vendor ID Register (offset: 0x00)

This register is reset by hard Reset.
Name
Device ID
Vendor ID

Status and Command Register (offset: 0x04)

This register is reset by PCIE Reset.
Name Bits
Detected Parity 31
Error
Signaled System 30
Error
Received Master 29
Abort
Received Target 28
Abort
Signaled Target 27
Abort
DEVSEL Timing 26:25
Master Data Parity 24
Error
Fast Back-to-back 23
capable
Reserved 22
66 MHz Capable 21
Capabilities List 20
Interrupt Status 19
Broadcom
®
January 29, 2016 • 5718-PG108-R
Bits Access Default Value
31:16 RO –
15:0 RO 0x14E4
Default
Access Value
RW2C 0x0
RW2C 0x0
RW2C 0x0
RW2C 0x0
RW2C 0x0
RO 0x0
RW2C 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x1
RO 0x0
Description
Default for BCM5717 (LAN Function 0): 0x1655
Default for BCM5718 (LAN Function 0): 0x1656
–
Description
When this bit is set, it indicates that the function has
received a poisoned TLP
This bit is set when a function sends an ERR_FATAL or
ERR_NONFATAL message and the SERR enable bit in
the command register is set
This bit is set when a requester receives a completion with
UR completion status
This bit is set when a requester receives a completion with
completer abort completion status.
This bit is set when a function acting as a completer
terminates a request by issuing Completer abort
completion status to the requester
Does not apply to PCIE
The master data parity error bit is set by a requester if the
parity error enable bit is set in its command register and
either of the following 2 conditions occur. If the requester
receives a poisoned completion if the requester poisons a
write request If the parity Error enable bit is cleared, the
master data parity error status bit is never set
Does not apply to PCIE.
These bits are reserved and tied low per the PCI
specification.
Does not apply to PCIE
This bit is tied high to indicate that the device supports a
capability list. The list starts at address 0x40.
Indicates this device generated an interrupt
PCI Configuration Registers
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