Serial Eeprom Address Register; Serial Eeprom Delay Register (Offset: 0X6848); Rx Cpu Event Enable Register (Offset: 0X684C) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Serial EEPROM Address Register

This 32-bit register is used by the RISCs in conjunction with the Serial EEPROM Data Register to read and/or
write serial EEPROM data. The address register specifies the address and the direction of the transfer. When
the transfer is complete (for either a read or a write), the complete bit is set.
To use this register pair to read the serial EEPROM, set the address and ensure the read/write bit is set in the
address register. Loop reading the address register until the complete bit is set. When it is read the data from
the data register. Clear the complete bit by writing the bit. No other transfer will occur when the complete bit is
set. The Device ID must be programmed to select the appropriate device (A2 must be 0 for 128K/256Kx8
device).
To use this register pair to write the serial EEPROM, place the data into the data register. Then write the address
into the address register ensuring that the write bit is clear. Loop reading the address register until the complete
bit is set. When it is, the write is complete. Clear the complete bit by writing the bit. No other transfer will occur
when the complete bit is set. It is the responsibility of software to control the timing between successive read/
write access to the serial EEPROM.
All registers reset are core reset unless specified.

Serial EEPROM Delay Register (offset: 0x6848)

This 32-bit RW register specifies the delay between the EEPROM access in 15 ns interval and is used for VPD
access. Since the requirement of back-to-back write for Serial EEPROMs is 10ms, firmware currently programs
this register to 0xA2C2A.

RX CPU Event Enable Register (offset: 0x684C)

Setting a bit in this register enables an interrupt to the CPU or the Event.
Name
Flash
VPD
Timer Reference Reached
ROM
HC Module
RX CPU Module
EMAC Module
Memory Map Enable Bit
Reserved
High Priority Mailbox
Low Priority Mailbox
DMA
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31 RW 0
30 RW 0
29 RW 0
28 RW 0
27 RW 0
26 RW 0
25 RW 0
24 RW 0
23 RW 0
22 RW 0
21 RW 0
20 RW 0
Serial EEPROM Address Register
Description
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Set by hardware, cleared by software.
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