BCM5718 Programmer's Guide
Bit
Name
1
SGMII 10/100 RX FIFO
FRE QUENCY LOCK
MODE
(forced high internally
when =>
sgmii_slave_mode and not
remote_lpbk)
0
AUTO-DETECT SGMII/
GBIC MODE
1Ch: Test 1000-X Register (Shadow Register Selector = "19h")
Bit
Name
15
WRITE ENABLE
14:10 SHADOW REGISTER
SELECTOR
9
USE COPPER SPEED
8
DLL BYPASS CLOCK
ENABLE
7
TX FIFO SGMII 10/100
EARLY PREAMBLE
MODE =>
towards SerDes link
partner
6
RX FIFO SGMII 10/100
EARLY PREAMBLE
MODE =>
towards copper link partner
5
BLOCK TXEN MODE
FOR dig1000x_tx_fifo =>
towards SerDes link
partner
4
RESERVED
3
FORCE TXFIFO ON
(dig1000x_tx_fifo)
towards SerDes link
partner
2
BYPASS PCS RECEIVE
Broadcom
®
January 29, 2016 • 5718-PG108-R
RW
Description
RW
1 = SGMII RX FIFO will assume that the SerDes
recovered clock and the local clock are
frequency locked. This will essentially bypass
the FIFO with the lowest possible latency in 10/
100 speeds
(useful for applications where the MAC/switch
and PHY are using the same crystal)
0 = normal operation
RW
1 = enable auto-detection between SGMII and
GBIC modes
0 = normal operation
RW
Description
RW
1 = write bits [9:0]
0 = read bits [9:0]
RW
Shadow Register Selector
RW
1 = force dig1000x speed to copper speed
(used to test FIFOs in 10/100 mode from GMII
pins)
0 = normal operation
RW
1 = enable dll bypass clock (tpin 11)
0 = disable dll bypass clock
RW
1 = enable transmitting early preamble in SGMII
10/ 100 mode in order to reduce latency in half-
duplex.
(TX FIFO)
0 = normal operation
RW
1 = enable transmitting early preamble in SGMII
10/ 100 mode in order to reduce latency in half-
duplex (RX FIFO).
0 = normal operation
RW
1 = block txen for 7 bytes after end of packet in
1000-X mode, 6.5 bytes in SGMII 10/100.
0 = normal operation
RW
write as 0, ignore on read
RW
1 = force TXFIFO to be always active in 1000X
0 = normal operation
RW
1 = bypass pcs receive
0 = normal operation
10h–1Fh Register Map Detailed Description
Default
0
0
Default
0
11001
0
0
0
0
0
0
0
0
Page 536
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