Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 28

BCM5718 Programmer's Guide
Jumbo Receive BD Producer Ring Replenish Threshold Register (offset: 0x2C1C) .......................... 373
Standard Replenish LWM Register (offset 0x2D00) ........................................................................... 373
Jumbo Replenish LWM Register (offset 0x2D04) ............................................................................... 374
BD Fetch Limit Register (Offset 0x2D08)..................................................................................... 375
Receive BD Completion Control Registers............................................................................................ 375
Receive BD Completion Mode Register (offset: 0x3000).................................................................... 375
Receive BD Completion Status Register (offset: 0x3004)................................................................... 375
NIC Jumbo Receive BD Producer Index Register (offset: 0x3008)..................................................... 376
NIC Standard Receive BD Producer Index Register (offset: 0x300C) ................................................ 376
Central Power Management Unit (CPMU) Registers ............................................................................. 376
CPMU Control Register (offset: 0x3600)............................................................................................. 376
Link Speed 10 MB/No Link Power Mode Clock Policy Register (offset: 0x3604)................................ 378
Link Speed 100 MB Power Mode Clock Policy Register (offset: 0x3608)........................................... 379
Link Speed 1000 MB Power Mode Clock Policy Register (offset: 0x360C) ........................................ 380
Link Aware Power Mode Clock Policy Register (offset: 0x3610) ........................................................ 381
D0u Clock Policy Register (offset: 0x3614)......................................................................................... 382
Link Idle Power Mode Clock Policy Register (offset: 0x3618)............................................................. 382
APE CLK Policy Register (offset: 0x361C).......................................................................................... 383
APE Sleep State Clock Policy Register (offset: 0x3620)..................................................................... 385
Clock Speed Override Policy Register (offset: 0x3624) ...................................................................... 386
Clock Override Enable Register (offset: 0x3628) ................................................................................ 386
Status Register (offset: 0x362C) ......................................................................................................... 387
Clock Status Register (offset: 0x3630)................................................................................................ 389
Clock Status Register (offset: 0x3630)................................................................................................ 389
GPHY Control/Status Register (offset: 0x3638) .................................................................................. 391
RAM Control Register (offset: 0x363C)............................................................................................... 392
Core Idle Detection De-Bounce Control Register (offset: 0x3648)...................................................... 393
PCIE Idle Detection De-Bounce Control Register (offset: 0x364C) .................................................... 394
Energy Detection De-Bounce Timer (offset: 0x3650).......................................................................... 394
DLL Lock Timer Register (offset: 0x3654)........................................................................................... 396
CHIP ID Register (offset: 0x3658)....................................................................................................... 396
Mutex Request Register (offset: 0x365C) ........................................................................................... 397
Mutex Grant Register (offset: 0x3660) ................................................................................................ 397
GPHY Strap Register (offset: 0x3664) ................................................................................................ 397
Padring Control Register (offset: 0x3668) ........................................................................................... 398
Flash Clock Policy Register (offset: 0x366C) ...................................................................................... 399
Link Idle Control Register (offset: 0x3670) .......................................................................................... 401
Link Idle Status Register (offset: 0x3674) ........................................................................................... 404
Top Level Miscellaneous Control 1 Register (offset: 0x367C) ............................................................ 405
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January 29, 2016 • 5718-PG108-R
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