1Ch: Clock Alignment Control Register (Shadow Register Selector = "03H") - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Bit Name
14:10 SHADOW REGISTER
SELECTOR
9 SD status
8 FORCE SD ON
7 INVERT SD PIN
6 CFC_INITFILTER
ENABLE
5 USE FILTERED SD
4 100FX MODE COPPER
PATH
3 RESERVED
2 BICOLOR LINK SPEED
LED MODE
1 LOST TOKEN FIX
DISABLE
0 LINK LED MODE
1Ch: Clock Alignment Control Register (Shadow Register Selector =
"03h")
Bit Name
15 WRITE ENABLE
14:10 SHADOW REGISTER
SELECTOR
9 GTXCLK delay bypass
disable (input delay only)
8 GMII CLOCK ALIGNMENT
STROBE
7 RXCLK ALIGNMENT
STROBE
Broadcom
®
January 29, 2016 • 5718-PG108-R
RW Description
RW Shadow Register Selector
RO 1= sd input active
RW 1= force sd on. disable sd pin input
RW 1 = invert sd pin
RW 1 = enable cfc_initFilter signal to control clock
gating of 1000t clocks. Do not gate off 1000t
clocks wherever cfiltercntl is initializing the filter.
RW 1= enable filter on sd input pin
RW 1 = enable 100BASE-FX on TRD+/- pins
0 = normal copper operation on MDI pairs
RW write as 0, ignore on read
RW 1 = enable Bicolor Link Speed led mode
LINKSPD[1:0] = speed
10 = 1000 base-t
01 = 100 base-t
11 = auto-negotiation, 10 base-t
RW When 0, enables lost token fix reset circuits
RW 1 = enable Link LED mode:
LINKSPD[1:0] = speed
00 = 1000 base-t
01 = 100 base-t
10 = 10 base-t
11 = auto-negotiation
SLAVE = active low link
0 = normal link/slave mode
RW Description
RW 1 = write bits [9:0]
0 = read bits [9:0]
RW Shadow Register Selector
RW 1 = do not bypass gtxclk delay
0 = bypass gtxclk delay
RW Delay value is latched into selected GMII clock
delay line on rising edge of this bit.
RW Delay value is latched into selected RX clock
delay line on rising edge of this bit.
10h–1Fh Register Map Detailed Description
Default
00010
0
0
0
0
0
0
0
0
1
0
Default
0
00011
0
0
0
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