Message Signaled Interrupt; Figure 51: Message-Signaled Interrupt Scheme - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
• DMAs data of received packets to the host.
• DMAs receive buffer descriptors to Receive Return Ring in the host memory.
• DMAs status block to the host memory.
• Generates an interrupt to request its device driver for processing.
The writes are posted and are actually performed at some later time by the PCI host bridge. When interrupt
service routine of device driver is executed, the driver reads the status block from the host memory and finds
that status block does not contain latest index information if the writes for status block are not performed by the
PCI host bridge yet. The scheme to resolve this problem is to do a dummy read of the Ethernet controller in the
beginning of the interrupt service routine. The dummy read has to traverse the same bridge that memory writes
from the Ethernet controller have to traverse to get to the host memory. The ordering rules for bridges dictate
that the bridge must flush its posted write buffers before permitting a read to traverse the bridge. As a result,
writes for status block are flushed to the host memory by the bridge before dummy read cycle is completed.

Message Signaled Interrupt

A simplified block diagram showing a possible MSI scheme is depicted in
BCM5718 Ethernet
Controller BCM5700
Host Memory
Host Memory
Similar example in traditional interrupt scheme is used again here to illustrate MSI concept. The Ethernet
controller receives one or more packets from the networks. The Ethernet controller does the following:
Broadcom
®
January 29, 2016 • 5718-PG108-R

Figure 51: Message-Signaled Interrupt Scheme

PCI Host
PCI Host Bridge
Bridge
Figure 51.
Interrupt
Interrupt
Controller
Controller
CPU
CPU
MSI
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