Phy Auto-Negotiation; Integrated Macs; Table 87: Integrated Mac Flow Control Registers - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

PHY Auto-Negotiation

The PHY encodes flow control capability into Fast Link Pulse (FLPs) bursts. Link partners will extract encoded
flow control capability from FLPs and then create a Link Code Word (LCW). The LCW is a message, which
contains a selector and technology ability field. The technology ability field contains a bit called
Pause_Operation_for Full_Duplex_Link (A5). Refer to Annex 28-B of the IEEE 802.3 specifications. The A5 bit
signifies that a link partner has implemented pause functionality. If both link partners support auto-negotiation,
they will further exchange data regarding flow control, using the next page bit in the LCW.
Auto-advertise is integrally tied to auto-negotiation. If link partner does not support pause functionality, the PHY
Auto_Negotation_Link_Partner_Ability_Register does not set the Pause_Capable bit. The Ethernet controller
should not send pause frames to this link partner since flow control is not implemented or disabled. The Ethernet
controller can still accept pause frames, but sending a pause frame does not yield a preferred result.

Integrated MACs

Table 86 on page 225 lists the flow control registers in the Ethernet controllers.
Register Bit(s) Name
Receive MAC Mode Enable_Flow_Control Enable automatic processing of
Transmit MAC Enable_Flow_Control Enable automatic processing of
Mode
MAC_RX_MBUF_ All 32 bits
Low_Water_Mark
Broadcom
®
January 29, 2016 • 5718-PG108-R

Table 87: Integrated MAC Flow Control Registers

Description
IEEE 802.3 flow control frames.
IEEE 802.3 flow control frames.
The number of internal buffers that
must be available before the RX
engine can accept a frame from the
wire.
Threshold value for initiating flow
control.
Flow Control
Cross Reference
See "Receive MAC Mode
Register (offset: 0x468)" on
page 322.
See "Transmit MAC Mode
Register (offset: 0x45C)" on
page 319.
See "Low Watermark
Maximum Receive Frame
Register (offset: 0x504)" on
page 327.
Page 226