Vlan Tag Register For Tcp Segmentation (Offset: 0Xcf0); Pre-Dma Command Exchange Register For Tcp Segmentation (Offset: 0Xcf4) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Invoke Processor
Don't Generate CRC
No Byte Swap

VLAN Tag Register for TCP Segmentation (offset: 0xCF0)

Name
Reserved
VLAN Tag
Pre-DMA Command Exchange Register for TCP Segmentation
(offset: 0xCF4)
Name
READY
PASS Status
SKIP Status
Unsupported_Mss Status
Reserved
BD Index
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
2 RW –
1 RW –
0 RW –
Default
Bits Access Value
31:16 RO 0
15:0 RW 0
Default
Bits Access Value
31 RW 0
30 RO 1
29 RW 0
28 RO 0
27:7 RO 0
6:0 RO 0
TCP Segmentation Control Registers
Description
Clears the Pass bit of the entry queued to the
SDCQ, so that SDC will invoke CPU.
• If the packet is created by hardware, this bit
will be the same as bit 9 of the flag field in
Send BD.
• If the packet is created by firmware, it will be
up to CPU whether it needs to post-process
the data.
Do not generate CRC.
Pass through Send Buffer Descriptor flag.
Set to disable endian byte swap on data from
PCIE bus.
Description
–
VLAN Tag to be inserted into the Frame Header
if bit 7 of DMA Flags register is set.
Description
The CPU sets this bit to tell SDI that DMA
address, length, flags, and VLAN tag are valid
and request is read to go.
The CPU polls this bit to be clear for the
completion of request.
0xCF4.31 is writable only if 0xCE8.15:0 is
nonzero.
If this bit is set to 0, the CPU will be responsible
for processing the buffer descriptor
The CPU sets this bit to 1 to inform the SDI that
the TCP Segmentation is completed, and the
BD_Index can be incremented.
–
–
The internal current buffer descriptor pointer that
the hardware/firmware is servicing.
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