Rdma Registers; Lso Read Dma Mode Register (Offset: 0X4800) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

RDMA Registers

All registers reset are core reset unless specified.

LSO Read DMA Mode Register (offset: 0x4800)

Name
Reserved
In-Band VLAN Tag Enable
Hardware IPv6 Post-DMA
Processing Enable
Hardware IPv4 Post-DMA
Processing Enable
Post-DMA Debug Enable
Address Overflow Error
Logging Enable
Disable Multiple Outstanding
Read DMA
Reserved
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:30 RO 0
29 RW 1
28 RW 0
27 RW 0
26 RW 0
25 RW 0
24 WO 0
23:18 RO 0
Description
–
In Band VLAN Tag Enable
1: Enable In_Band VLAN Tag
0: Disable In-Band VLAN Tag
Enables hardware processing of LSO IPv6
packets. This bit has no effect on Post-DMA
processing of IPv4 packets.
Enables hardware processing of LSO IPv4
packets. This bit has no effect on Post-DMA
processing of IPv6 packets.
When this bit is set, the Send Data Completion
State Machine will be halted if the Post-DMA bit
of the Send BD is set.
This bit when set, enables the address overflow
error to be generated when the DMA Read
Engine performs a DMA operation that crosses a
4G boundary. This error is reported in bit 3 of the
DMA Read Status Register. Subsequently, this
will generate an internal event to interrupt the
internal CPU and the DMA Read Engine will lock
up after detecting this error. So it is
recommended that this bit should not be set by
firmware or software.
1: Enable Address Overflow Error Logging
0: Disable Address Overflow Error Logging.
0: Enable Multiple Outstanding Read DMA
1: Disable Multiple Outstanding Read DMA
This bit will always read back as 0, even if written
as 1.
This feature should be disabled in 5718 A0 Chip
–
RDMA Registers
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