BCM5718 Programmer's Guide
DEVICE_CAPABILITY_2 – 0xd0
Name
Unused1
LTR_MECHANISM_SUPPORT
ED
Unused0
CMPL_TIMEOUT_DISABL_
SUPPORTED
CMPL_TIMEOUT_RANGES_
SUPPORTED
DEVICE_STATUS_CONTROL2 – 0xd4
Name
DEVICE_STATUS_2
Unused
LTR_MECHANISM_ENABLE
IDO_CPL_ENABLE
IDO_REQ_ENABLE
Unused0
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits
Access
Value
31:12
RO
0
11
RO
0
10:5
RO
0
4
RO
0x1
3:0
RO
0xf
Default
Bits
Access
Value
31:16
RO
0
15:11
RO
0
10
RW
0
9
RW
0
8
RW
0
7:5
RO
0
PCI Configuration Registers
Description
–
Latency Tolerance Reporting Mechanism
Supported, Programmable through register
space. This field will read 1, when bit 5 of
ext_cap_ena field in private register space is set.
–
Completion Timeout Disable Supported,
Programmable through register space
Path= i_cfg_func.i_cfg_private
Completion Timeout Ranges Supported.
Programmable through register space
Path= i_cfg_func.i_cfg_private
Value
Name
Description
15
ABCD
Ranges A, B, C, and D
255
–
end_of_table
Description
Placeholder for Gen2
Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
–
Latency Tolerance Reporting Mechanism
Enable, This field is writeable, when bit 5 of
ext_cap_ena field in private register space is set.
This bit is RW only in function 0 and is RsvdP for
all other functions.
IDO Completion Enable, This field is writeable,
when bit ido_supported bit of private
device_capability_2 register is set. When this bit
is set, function is permitted to set ID based
Ordering Attribute of Completions it returns.
IDO Request Enable, This field is writeable,
when bit ido_supported bit of private
device_capability_2 register is set. When this bit
is set, function is permitted to set ID based
Ordering Attribute of Requests it initiates.
–
Page 297
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