Device State D0 (Active); Device State D3 (Hot); Device State D3 (Cold); Wake On Lan - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Device State D0 (Active)

Host software has initialized the MAC hardware blocks. The RX and TX data paths are ready to send/receive
Ethernet packets. The PCI block is available to DMA packets to host memory. This is a full power ACPI
operational state. Host software/drivers must follow the initialization procedure (see
Registers" on page 136) to move the MAC into a D0 active state.
When the BCM5718 family NetXtreme devices detect that main power is lost and it is still in the D0 state, it will
reset itself to the D3 (Cold) state and then operate in 10/100 mode, like the OOB WOL state.

Device State D3 (Hot)

The MAC's configuration space and memory mapped I/O blocks are accessible in D3 hot state. The PCI I/O
drivers are still powered by slot power in this state. However, host software has switched the MAC to use PCI
Vaux for VDD_CORE and VDD_IO. GPIO pins 0, 1, and 2 are configured before the transition to this state. The
RX RISC processor clock has been stopped in this state. The core clock remains active so PCI transactions
may be processed by the MAC. This is a low-power state where some key components have been powered
down. The physical layer auto-advertises 10 Mbps capability in this state, and link is set to 10 Mbps half-duplex
or full-duplex. The PHY is configured for WOL mode. WOL pattern filters are initialized and active; the MAC will
™
process Magic Packets
driver does not influence the PCI Vaux or Slot power supply.
Note: The drivers should use configuration cycles (not the memory write cycles) to write to the PMCSR
register at offset 0x4C for putting the device in D3 Hot state.

Device State D3 (Cold)

The MAC is completely powered by PCI Vaux in D3 cold. PCI configuration space and memory mapped I/O are
not available. The only portion of the MAC active is the WOL pattern and Magic Packet filters
assert a PME in this state and indicate to the host bridge that a wake up event has occurred. The host bridge
will normally provide PCI Slot power and then reset the device. GPIO pins 0, 1, and 2 are configured the same
as D3 hot. Host software does not differentiate between D3 hot/cold. The MAC and PHY will not consume more
than 375 mA in this mode. The integrated PHY must negotiate for 10 Mbps half/duplex speed. The PHY WOL
mode is configured.
Note: The PCIe devices support the PCIe power management which is compatible with PCI bus power
management.

Wake on LAN

See "Wake on LAN Mode/Low-Power" on page
™
1. Magic Packet is a registered trade mark of AMD.
Broadcom
®
January 29, 2016 • 5718-PG108-R
. The host chipset implements the power management policy for the PCI bus; the MAC
212.
Power Management
"Initializing the MAC Hash
1
. The MAC will
Page 190