BCM5718 Programmer's Guide
Power Management Capability Register (offset: 0x48)
This register is reset by hard Reset.
Name
Bits
PME Support
31:27
D2 Support
26
D1 Support
25
Aux Current
24:22
DSI
21
Reserved
20
PME Clock
19
Version
18:16
PM Next
15:8
Capabilities
PM Capability
7:0
ID
Power Management Control/Status Register (offset: 0x4C)
This register is reset by Hard Reset.
Name
Bits
Access
PM Data
31:24
RO
FW-RW
Reserved
23:16
RO
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Access
Value
Description
RO
0x08 if no
Indicates the power states in which the device may assert
aux
PME. A 0 for any bit indicates that the device is not capable of
asserting the PME pin signal while in that power state.
0x18 if aux
Bit 27: PME can be asserted from D0
Bit 28: PME can be asserted from D1
Bit 29: PME can be asserted from D2
Bit 30: PME can be asserted from D3H
Bit 31: PME can be asserted from D3C (default depends on
the presence of Aux power)
RO
0x0
Indicates whether the device supports the D2 PM state. This
device does not support D2; hardwired to 0
RO
0x0
Indicates whether the device supports the D1 PM state. This
device does not support D1
FW-RW
RO
0x0
This device supports the data register for reporting Aux
Current requirements so this field is N/A.
FW-RW
RO
0x0
Indicates that the device requires device specific initialization
(beyond PCI configuration header) before the generic class
device driver is able to use it. This device hardwires this bit to
0 indicating that DSI is not necessary
RO
0x0
–
RO
0x0
Indicates that the device relies on the presence of the PCI
clock for PME operation. This device does not require the PCI
clock to generate PME. Therefore, the bit is hardwired to 0
RO
0x3
A value of 011b indicates that this function complies with
revision 1.2 of the PCI PM specification.
RO
0x58
Points to the next capabilities block which is Broadcom Vendor
Specific Capability Header
RO
0x01
Identifies this item as Power management capabilities
Default
Value
Description
0x00
Contains the power management data indicated by the Data
Select field in PMCSR
0x00
–
PCI Configuration Registers
Page 279
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