Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 144

BCM5718 Programmer's Guide
43. Enable and clear statistics by setting the Clear_TX_Statistics, Enable_TX_Statistics, Clear_RX_Statistics,
and Enable_TX_Statistics bits in the Ethernet Mac Mode register (see
0x400)" on page 310).
44. Delay 40 microseconds.
45. Configure the General Miscellaneous Local Control register (see
(offset: 0x6808)" on page
any of the attention bits in the CPU event register are asserted.
46. Delay 100 microseconds.
47. Configure the Write DMA Mode register (see
following bits are asserted:
• Enable (starts the functional block)
• Write_DMA_PCI_Target_Abort_Attention_Enable
• Write_DMA_PCI_Master_Abort_Attention_Enable
• Write_DMA_PCI_Parity_Attention_Enable
• Write_DMA_PCI_Host_Address_Overflow_Attention_Enable
• Write_DMA_PCI_FIFO_Overerrun_Attention_Enable
• Write_DMA_PCI_FIFO_Underrun_Attention_Enable
• Write_DMA_PCI_FIFO_Overwrite_Attention_Enable
• Write_DMA_Local_Memory_Read_Longer_Than_DMA_Length
48. Set bit-29 of the Write DMA Mode register (see
to enable the host coalescence block fix that configures the device to send out status block update before
the interrupt message.
49. Delay 40 microseconds.
50. Set register 0x4900[2] = 1 to prevent DMA overruns for BD read DMA engine. This enables a hardware
function which limits all BD fetches to 256 bytes or less.
51. Configure the Read DMA Mode register (see
page 433). The following bits are asserted:
• Enable—start functional block
• Read_DMA_PCI_Target_Abort
• Read_DMA_PCI_Master_Abort
• Read_DMA_PCI_Parity_Error
• Read_DMA_PCI_Host_Overflow_Error
• Read_DMA_PCI_FIFO_Overrun_Error
• Read_DMA_PCI_FIFO_Underrun_Error
• Read_DMA_PCI_FIFO_Overread_Error
• Read_DMA_Local_Memory_Write_Longer_Than_DMA_Length
52. Delay 40 microseconds.
53. Set 0x4800[24] = 0 to Allows multiple outstanding read requests from the non-LSO read DMA engine.
54. Set 0x4800[17:16] = 11b to Allows 4KB burst length reads for Jumbo/LSO network frames.
Broadcom
®
January 29, 2016 • 5718-PG108-R
471). Set the Interrupt_On_Attention bit for MAC to assert an interrupt whenever
"Write DMA Mode Register (offset: 0x4C00)" on page
"Write DMA Mode Register (offset: 0x4C00)" on page
"LSO Read DMA Mode Register (offset: 0x4800)" on
Initialization Procedure
"EMAC Mode Register (offset:
"Miscellaneous Local Control Register
449). The
449)
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