Pcie Capabilities Registers; Pcie_Capability - 0Xac - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

PCIe Capabilities Registers

PCIE_CAPABILITY – 0xac
Name
unused0
MSG_NUM
SLOT_IMPLEMENTED
TYPE
VER
PCIE_NEXT_CAP_PTR
PCIE_CAP_ID
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:30 RO 0
29:25 RO 0
24 RO 0
23:20 RO 0
19:16 RO 0x2
15:8 RO 0
7:0 RO 0x10
Description
–
Interrupt Message Number: Indicate which MSI/
MSI-X vector is used for the interrupt message
generated in association with any of the status bits
of this capability structure. For MSI, the value in
this register indicates the offset between the base
Message Data and the interrupt message that is
generated. For MSI-X, the value in this register
indicates which MSI-X Table entry is used to
generate the interrupt message. The entry must
be one of the first 32 entries even if the function
implements more than 32 entries.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Slot Implemented. This register is not supported.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Slot Implemented. This register is not supported.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Capability Version. PCI Express Capability
structure version number. These bits are
hardwired to 2h. Path= cfg_defs
This registers contains the pointer to the next PCI
capability structure.
Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
This register contains the PCIExpress Capability
ID. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
PCI Configuration Registers
Page 289