Table 38: Recommended Bcm57Xx Ethernet Controller Memory Pool Watermark Settings; Table 39: Recommended Bcm57Xx Ethernet Controller Low Watermark Maximum Receive Frames Settings - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
This step is relevant when TCP/UDP checksum calculations are offloaded to the device. The device driver
may optionally disable receive and transmit pseudo header checksum calculations by the device by setting
the Receive_No_PseudoHeader_Checksum and Send_No_PseudoHeader_Checksum bits in the General
Mode Control register (see
Send_No_PsuedoHeader_Checksum bit is set, the host software must seed the correct pseudo header
checksum value in TCP/UDP checksum field. Similarly, if the Receive_No_PsuedoHeader_Checksum bit is
set, the device driver must calculate the pseudo header checksum and add it to the TCP/UDP checksum
field of the received packet.
11. Configure MAC Mbuf memory pool watermarks
on page 430, and "Read DMA MBUF High Watermark Register (offset: 0x4418)" on page
has run hardware simulations on the Mbuf usage and strongly recommends the settings shown in
These settings/values establish proper operation for 10/100/1000 speeds.

Table 38: Recommended BCM57XX Ethernet Controller Memory Pool Watermark Settings

Register
MAC RX Mbuf Low Watermark (0x4414)
Mbuf High Watermark (0x4418)
Note: The Low WaterMark Max Receive Frames register (0x504) specifies the number of good frames to
receive after RxMbuf Low Watermark has been reached. The driver software must make sure that the MAC
RxMbuf Low WaterMark is greater than the number of Mbufs required for receiving the number of frames as
specified in 0x504. The first Mbuf in the Mbuf chain of a frame will have 80 bytes of packet data while each of
the subsequent Mbufs [except the last Mbuf] will have 120 bytes for packet data. The last Mbuf in the chain will
have the rest of the packet data which can be up to 120 bytes.
12. Configure flow control behavior when the Rx Mbuf low watermark level has been reached
Table 39: Recommended BCM57XX Ethernet controller Low Watermark Maximum Receive Frames
Register
Low Water Mark Maximum Receive Frames
(0x504)
13. Enable the buffer manager by setting the Enable and Attn_Enable bits in the Buffer Manager Mode register
(see "Buffer Manager Mode Register (offset: 0x4400)" on page
internal allocation of memory resources for send and receive traffic.
14. Set the BD Ring Replenish threshold for the RX Producer Ring. The threshold values indicate the number
of buffer descriptors that must be indicated by the host software before a DMA is initiated to fetch additional
receive descriptors in order to replenish used receive descriptors. The recommended configuration value for
the standard receive BD Ring replenish threshold is 0x19 (see
Replenish Threshold Register (offset: 0x2C18)" on page
15. Initialize the standard receive Buffer Ring. Host software must write the Ring Control Block structure (see
"Ring Control Block" on page
BD Ring RCB Registers" on page
based on allocation routines specific to the OS.
16. Initialize the Max_len/Flags Receive Ring RCB register (0x2458).
Broadcom
®
January 29, 2016 • 5718-PG108-R
"Mode Control Register (Offset
("MAC RX MBUF Low Watermark Register (offset: 0x4414)"
Standard Ethernet Frames
0x2A
0xA0
Settings
Recommended Value
1
107) to the standard receive BD Ring RCB register (see
366"). Host software must initialize the host physical memory address
0x6800)"). If the
428). The buffer manager handles the
"Standard Receive BD Producer Ring
373)
Initialization Procedure
430). Broadcom
Table 38.
(seeTable 39).
"Standard Receive
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