Miscellaneous Configuration Register (Offset: 0X6804) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
No Frame Cracking
IOV Mode Enable
Legacy
Byte Swap for B2HRX Data
Word Swap for B2HRX Data
Word Swap Data
Byte Swap Data
FLR state
Word Swap BD
Byte Swap BD
Reserved

Miscellaneous Configuration Register (offset: 0x6804)

Name
ID7
ID6
Disable GRC Reset on PCIE
block
ID5
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
9 RW 0
8 RW 0
7:0
7 RW 0
6 RW 0
5 Host- 0
RW NIC-
R
4 Host- 0
RW NIC-
R
3 RO 0
2 Host- 0
RW NIC-
R
1 Host- 0
RW NIC-
R
0 RO 0
Default
Bits Access Value
31 RO ID7
30 RO ID6
29 RW 0
28 RO ID5
Description
Turn off all frame cracking functionality in both
the read DMA engine and the MAC receive
engine. On receive, the TCP/UDP checksum
field is replaced by raw checksum for the whole
frame except the Ethernet header.
On transmit, IP and TCP/UDP checksum
generation is always disabled when this bit is set.
Also, the raw checksum is calculated over the
entire frame except the Ethernet header and
CRC.
When this bit is written 1, the chip enters IOV-
MODE.
When this bit is written 0, the chip operates in
legacy mode.
This bit must only be configured during boot-up
and must not be changed afterwards.
Defined by Legacy
This bit must be 1 for proper B2HRX operation in
case of Little-Endian Host machines.
This bit must be 1 for proper B2HRX operation in
case of Little-Endian Host machines.
Word swap data when DMAing it across the
PCIE bus.
Byte swap data when DMAing it across the PCIE
bus.
When this bit is set, it means PCIE is in FLR state
for this MAC core.
Word swap BD structure when DMAing them
across the PCIE bus.
Byte swap BD structure when DMAing them
across the PCIE bus.
–
Description
Bond ID 7
Bond ID 6
Setting this bit will prevent reset to PCIE block.
Bond ID 5
GRC Registers
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