Gigabit Pcs Test Register (Offset: 0X440); Transmit 1000Base-X Auto-Negotiation Register (Offset: 0X444); Receive 1000Base-X Auto-Negotiation Register (Offset: 0X448); Mii Communication Register (Offset: 0X44C) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Gigabit PCS Test Register (offset: 0x440)

Name
Reserved

Transmit 1000BASE-X Auto-Negotiation Register (offset: 0x444)

Name
Reserved

Receive 1000BASE-X Auto-Negotiation Register (offset: 0x448)

Name
Reserved

MII Communication Register (offset: 0x44C)

Name
Reserved
Start/Busy
Read Failed
Command
PHY Addr
Register Address
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:0 RO 0
Default
Bits Access Value
31:0 RO 0
Default
Bits Access Value
31:0 RO 0
Default
Bits Access Value
31:30 RO 0
29 RW 0
28 RO 0
27:26 RW 0
25:21 RW 0
20:16 RW 0
Ethernet MAC (EMAC) Registers
Description
–
Description
–
Description
–
Description
–
Set this bit to start a transaction.
While it is high, it indicates that the current
transaction is still ongoing.
If enabled, generates an attention via EMAC
Status Register MI Completion bit (bit 22).
When set, the transceiver device did not driver
the bus during the attempted read transaction.
Valid after the Start/Busy bit is cleared.
These bits specify the transaction type:
11: Undefined
10: Read command
01: Write command
00: Undefined
0x8: SGMII SerDes Port0.
0x9: SGMII SerDes Port1.
as strapped: External PHY Port0
as strapped: External PHY Port1
Address of the register to be read or written.
Page 317