Rx Risc Program Counter (Offset: 0X501C); Rx Risc Hardware Breakpoint Register (Offset: 0X5034) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Data access stall
Reserved
RX RISC Halted
Register Address Trap
Memory Address Trap
Bad Memory Alignment
Invalid Instruction Fetch
Invalid Data Access
Page 0 Instruction Reference 4
Page 0 Data Reference
Invalid Instruction
Halt Instruction Executed
Hardware Breakpoint

RX RISC Program Counter (offset: 0x501C)

The program counter register can be used to read or write the current Program Counter of the each CPU. Reads
can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any
pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are
ignored.

RX RISC Hardware Breakpoint Register (offset: 0x5034)

This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals
the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate
stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the
byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit.
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
14 RO 0
13:11 RO 0
10 RO 0
9 W2C 0
8 W2C 0
7 W2C 0
6 W2C 0
5 W2C 0
W2C 0
3 W2C 0
2 W2C 0
1 W2C 0
0 W2C 0
Description
The processor is currently stalled due to a data
access.
–
The RX RISC was explicitly halted via bit 10 in
the RX RISC Mode register.
A signal was received from the Global Resources
block indicating that this processor accessed a
register location that triggered a software trap.
The GRC registers are used to configure register
address trapping.
A signal was received from the Memory Arbiter
indicating that some BCM5700 block, possibly
this processor, accessed a memory location that
triggered a software trap. The MA registers are
used to configure memory address trapping.
Load or Store instruction was executed with the
least significant two address bits not valid for the
width of the operation (e.g., Load word or Load
Half-word from an odd byte address).
Program Counter (PC) is set to invalid location in
processor address space.
Data reference to illegal location.
When enabled in mode register, indicates the
address in the PC is within the lower 256 bytes of
SRAM.
When enabled in mode register, indicates data
reference within lower 256 bytes of SRAM.
Invalid instruction fetched.
A halt-type instruction was executed by the RX
RISC.
When enabled in mode register, indicates
hardware breakpoint has been reached.
RX-CPU Registers
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