Mii Status Register (Offset: 0X450); Mii Mode Register (Offset: 0X454) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Transaction Data

MII Status Register (offset: 0x450)

Name
Reserved
Mode 10 Mbps
Link Status

MII Mode Register (offset: 0x454)

Name
Reserved
MII Clock Count
Constant MDIO/MDC clock
speed.
Reserved
PHY Address
Port polling
Reserved
Auto_control
Use Short Preamble
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
15:0 RW 0
Default
Bits Access Value
31:2 RO 0
1 RW 0
0 RW 0
Default
Bits Access Value
31:21 RO 0
20:16 RW 0Ch
15 RW 0
14:10 RO 0
9:5 RW 1
4 RW 0
3 RO 0
2 RW 0
1 RW 1
Ethernet MAC (EMAC) Registers
Description
When configured for a write command, the data
stored at this location is written to the PHY at the
specified PHY and register address.
During a read command, the data returned by the
PHY is stored at this location.
Description
–
When read, a value of 1 indicates the transceiver
device is operating in 10 Mbps mode
The bit will generate an attention if enabled.
Indicates status of the link on the transceiver
device.
When read, a value of 1 indicates the transceiver
is linked
Description
–
Counter to divide CORE_CLK (62.5 MHz) to
generate the MI clock.
The formula is:
MI Clock = CORE_CLK/2/(MI Clock Count + 1).
Enable ~500Khz constant MII management
interface (MDIO/MDC) frequency regardless
core clock frequency.
1: Enable
0: Disable
–
This field specifies the PHY Address.
Set to enable autopolling of the transceiver link
information from the MII management interface.
If cleared, the device will obtain the link status
information from the state of the LINKRDY input
signal.
–
–
Use short preamble while polling, if set.
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