BCM5718 Programmer's Guide
DEVICE_CAPABILITY – 0xb0
Name
unused3
FLR_CAP_SUPPORTED
CAPTURED_SLOT_PWR_S
CALE
CAPTURED_SLOT_PWR_V
AL
unused2
ROLE_BASED_ERR_RPT
unused1
L1_ACCEPTABLE_LATENCY 11:9
L0S_ACCEPTABLE_LATENC
Y
EXTENDED_TAG_SUPPOR
T
unused0
MAX_PL_SIZE_SUPPORTE
D
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits
Access
Value
31:29
RO
0
28
RO
0
27:26
RO
0
25:18
RO
0
17:16
RO
0
15
RO
0x1
14:12
RO
0
RO
0x6
8:6
RO
0x6
5
RO
0
4:3
RO
0
2:0
RO
0x1
Description
–
FLR capability is advertized when flr_supported
bit in private device_capability register space is
set.
Specifies the scale used for the Slot Power Limit
Value. It is set by the Set_Slot_Power_Limit
Message. This field is not set for Root ports
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
Specifies the upper limit on power supplied by
slot. It is set by the Set_Slot_Power_Limit
Message. This field is not set for Root ports.
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
–
Indicate device is conforming to the ECN, PCI
Express Base Specification, Revision 1.1., or
subsequent PCI Express Base Specification
revisions. Path= i_cfg_func.i_cfg_private
–
Endpoint L1 Acceptable Latency. These bits are
programmable through register space. The bits
should be 0 for Root ports.
Path= i_cfg_func.i_cfg_private
Endpoint L0s Acceptable Latency. These bits are
programmable through register space. The value
should be 0 for root ports.
Path= i_cfg_func.i_cfg_private
Extended Tag Field Support. This bit is
programmable through register space. This
capability is not currently supported.
Path= i_cfg_func.i_cfg_private
Max Payload Size Supported. These bits are
programmable from the register space and default
value is based on define in version.v file. Path=
i_cfg_func.i_cfg_private
PCI Configuration Registers
Page 290
Need help?
Do you have a question about the NetXtreme/NetLink BCM5718 Series and is the answer not in the manual?
Questions and answers