Msi-X Cognizant Host Coalescing; Legacy Host Coalescing Parameters; Receive Coalescing Ticks Register (Offset: 0X3C08) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide MSI-X Plumbing

MSI-X Cognizant Host Coalescing

After sending a complete Transmit packet to the wire, the controller updates the Send BD Ring consumer index
internally. Similarly, after moving each full Received packet to the host memory, the controller updates its internal
copy of the Rx Return Ring producer index. The controller notifies the host software or the network stack of such
consumer and producer index updates by DMAing the Status Block and then sending an interrupt to the Host
CPU.
Host software does not necessarily need to get indication for every packet received from the network, nor does
it need to get completion for every packet sent to the wire. Heavy interrupt processing would degrade host CPU
performance. However, the stack must communicate with application processes in a timely manner to keep up
with network bandwidth demanded by the application. Thus, host software must have control in regulating—
however coarsely—when and how often it gets interrupts from the controller. The controller, in turn,
accumulates update events. When the accumulation reaches a threshold value, as configured by the host
software, the controller sends an interrupt. This scheme is known as interrupt coalescing or host coalescing.
Legacy NetXtreme architecture already offers a set of Host Coalescing (HC) Parameters.

Legacy Host Coalescing Parameters

This section lists the legacy set of host coalescing parameters that NetXtreme already offered prior to BCM5718
family.

Receive Coalescing Ticks Register (Offset: 0x3c08)

The value in this register can be used to control how often the status block is updated (and how often interrupts
are generated) due to receiving packets. The value in this register controls how many ticks, in units of 1 µs each,
get loaded in an internal receive tick timer register. The timer is reset to the value of this register and starts
counting down after every status block update (regardless of the reason for the status block update). The timer
is reset only after status block updates, and is not reset after any given packet is received. When the timer
reaches 0, it is considered to be in the expired state. When the counter is in the expired state, a status block
update will occur if a packet had been received and copied to host memory (via DMA) since the last status block
update.
This register must be initialized by host software. A value of 0 in this register disables the receive tick coalescing
logic. In this case, status block updates occur for receive events only if the Receive Max Coalesced BD value
is reached. Status block updates for other reasons (e.g., transmit events) also include any updates to the receive
indices. By setting the value in this register to a high number, a software device driver can reduce the number
of status block updates and interrupts that occur due to receiving packets. This generally increases performance
in hosts that are under a high degree of stress and whose RISCs are saturated due to handling a large number
of interrupts from the network controller. For host environments where receive interrupt latency must be very
low, and the host is not close to saturation, it is recommended that this register be set to 1.
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January 29, 2016 • 5718-PG108-R Page 253