Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 31

BCM5718 Programmer's Guide
Non-LSO Read DMA Flow Reserved Control Register (offset: 0x4B78) ............................................ 447
Non-LSO Read DMA Corruption Enable Control Register
(offset: 0x4B7C) .............................................................................................................................. 448
Write DMA Registers ................................................................................................................................ 449
Write DMA Mode Register (offset: 0x4C00) ........................................................................................ 449
Write DMA Status Register (offset: 0x4C04)....................................................................................... 450
RX-CPU Registers .................................................................................................................................... 451
RX RISC Mode Register (offset: 0x5000) ........................................................................................... 451
RX RISC Status Register (offset: 0x5004) .......................................................................................... 452
RX RISC Program Counter (offset: 0x501C)....................................................................................... 453
RX RISC Hardware Breakpoint Register (offset: 0x5034)................................................................... 453
VRQ Statistics........................................................................................................................................... 454
VRQ Filter Set Registers .......................................................................................................................... 455
VRQ Mapper Registers............................................................................................................................. 456
VRQ Enable Register (Offset 0x560) ........................................................................................... 458
RX Mail Box Registers for VRQ ................................................................................................... 458
Perfect Match Destination Address Registers....................................................................................... 459
VRQ_PERFECT_MATCH[4-23]_HIGH_REG (Offsets: 0x5690, 0x5698, 0x56A0 ... 0x5728) .......... 459
VRQ_PERFECT_MATCH[4 - 23]_LOW_REG (Offsets: 0x5694, 0x569C, 0x56A4 ... 0x572C)........ 460
Low Priority Mailboxes ............................................................................................................................ 460
Interrupt Mailbox 0 Register (offset: 0x5800) ...................................................................................... 460
Other Interrupt Mailbox Register (offset: 0x5808-0x5818) ................................................................. 460
General Mailbox Registers 1-8 (offset: 0x5820-0x5824) .................................................................... 461
Receive BD Standard Producer Ring Index Register (offset: 0x5868)................................................ 461
Receive BD Jumbo Producer Ring Index Register (offset: 0x5870-5877) .......................................... 461
Receive BD Return Ring 0 Consumer Index Register
(offset: 0x5880-0x5887) .................................................................................................................. 461
Receive BD Return Ring 1 Consumer Index Register
(offset: 0x5888-0x588F) .................................................................................................................. 461
Receive BD Return Ring 2 Consumer Index Register
(offset: 0x5890-0x5897) .................................................................................................................. 462
Receive BD Return Ring 3 Consumer Index Register
(offset: 0x5898-0x589F) .................................................................................................................. 462
Send BD Ring Host Producer Index Register (offset: 0x5900) ........................................................... 462
Send BD Ring NIC Producer Index Register (offset: 0x5980)............................................................. 463
Flow Through Queues.............................................................................................................................. 463
FTQ Reset Register (offset: 0x5C00).................................................................................................. 464
MAC TX FIFO Enqueue Register (offset: 0x5CB8)............................................................................. 465
RXMBUF Cluster Free Enqueue Register (offset: 0x5CC8) ............................................................... 465
RDIQ FTQ Write/Peak Register (offset: 0x5CFC)............................................................................... 465
Broadcom
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January 29, 2016 • 5718-PG108-R
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