Eav Ref Clock Control Reg [Offset 0X6908] - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

EAV REF CLOCK CONTROL REG [Offset 0x6908]

This register controls the EAV Reference Counter and the TimeSync related GPIO pins. Each MAC's 1588 HW
owns a dedicated TimeSync_GPIO pin which may be connected to any of its four Snap-shot/WatchDog HW
logic. If a MAC needs to use more pins beyond its TimeSync_GPIO pin, it may use any or all of the four
APE_GPIO[3:0] pins – note that these pins are shared among APE HW and four MAC-1588 HW. Thus a
platform must design-in these pins and have individual BootCode or FW configure this register and APEGPIO
register accordingly.
Note: HW behavior shall be indeterminate in case of conflicting or duplicate assignment of GPIO pins
to the same resource. A platform design MUST allocate its dedicated TimeSync_GPIO pin first before
using any pin from APE_GPIO shared pool (we are talking PCB/Hardware design here).
Name
Reserved
APE_GPIO[3] Mapping
APE_GPIO[2] Mapping
APE_GPIO[1] Mapping
APE_GPIO[0] Mapping
TimeSync_GPIO
Mapping
Reserved
Reset on Network Link
Down -> Up
Reset on Network Link
Up -> Down
Reset on GRC Reset and
PCIe FLR
Reset on PCIe reset
Reserved
Resume EAV Ref Count 2
Broadcom
®
January 29, 2016 • 5718-PG108-R
Bits Access Default Value Description
31:30 RO 00
29:27 RW 000
26:24 RW 000
23:21 RW 000
20:18 RW 000
17:16 RW 00
15:12 RO 0x0
11 RW 0
10 RW 0
9 RW 0
8 RW 0
7:3 RO 0x0
W1C 0
–
Same as below
Same as below
Same as below
An APE_GPIO[n] pin is mapped to 1588 input/output
via this field:
000 => Do not use APE_GPIO[n] pin
001 => Reserved
010 => Reserved
011 => Reserved
100 => Use as Snap-Shot[0] Input Trigger
101 => Use as Snap-Shot[1] Input Trigger
110 => Use as Time Watchdog[0] Output
111 => Use as Time Watchdog[1] Output
The MAC/Port dedicated TimeSync_GPIO pin is
mapped via this field:
00 => Use as Snap-Shot[0] Input Trigger
01 => Use as Snap-Shot[1] Input Trigger
10 => Use as Time Watchdog[0] Output
11 => Use as Time Watchdog[1] Output
Reset on GRC Reset pulse
Reset on de-asserting edge of PCIe Reset
Time Sync Registers
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