Vrq Flush Timer Register (Offset: 0X2414); Rdi B2Hrx Hardware Debugging Register (Offset: 0X2418); Jumbo Producer Ring Host Address High Register (Offset: 0X2440) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
VRQ hardware Flush enable

VRQ Flush Timer Register (offset: 0x2414)

Name
IOV Flush Timer

RDI B2HRX Hardware Debugging Register (offset: 0x2418)

Name
Legacy

Jumbo Producer Ring Host Address High Register (offset: 0x2440)

Name
Host Address High
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
0 RW 0x0
Default
Bits Access Value
31:0 RW 0x0
Default
Bits Access Value
31:0 RO 0x0
Default
Bits Access Value
31:0 RW 0
Receive Data and Receive BD Initiator Control Registers
Description
This value will be loaded into a count-down
counter triggered by a falling-edge of any bit of
VRQ Enable register (0x560). The count-down is
based on internal CORE_CLK. The purpose of
this counter is to allow hardware to drain out
certain pending DMA requests within WDMA
pipeline and PCIE core. Once the timer expires,
hardware shall invoke the Automatic VRQ Flush
Procedure. A value 0x0 in this register effectively
zeroes this timer count.
Description
This value will be loaded into a count-down
counter triggered by a falling-edge of any bit of
VRQ Enable register (0x560). The count-down is
based on internal CORE_CLK. The purpose of
this counter is to allow hardware to drain out
certain pending DMA requests within WDMA
pipeline and PCIE core. Once the timer expires,
hardware shall invoke the Automatic VRQ Flush
Procedure. A value 0x0 in this register effectively
zeroes this timer count.
Description
RDI internal B2HRX status.
Description
The host ring address is the host address of the
first ring element.
The host ring address is in host address format.
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