Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

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Programmer's Guide

BCM5718

NetXtreme

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BCM5718 Family

Programmer's Guide

5718-PG108-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203

January 29, 2016

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Page 1 Programmer’s Guide BCM5718 ® ® NetXtreme /NetLink BCM5718 Family Programmer’s Guide 5718-PG108-R 5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 January 29, 2016...
Page 2 • “Send Rings” on page 106 • “Initialization Procedure” on page 140 • Table 49: “GPIO Usage for Power Management for Broadcom Drivers,” on page 192 • Table 101: “Multiple Send Ring Mail Boxes,” on page 357 • “Send BD Ring Host Producer Index Register (offset: 0x5900)” on page 465 •...
Page 3 “VRQ Filter Set Registers” on page 461 • “VRQ Mapper Registers” on page 462 • “Base Address Register 5 (offset: 0x20)” on page 276 • “Base Address Register 6 (offset: 0x24)” on page 277 Broadcom ® January 29, 2016 • 5718-PG108-R Page 3...
Page 4 “Receive Max Coalesced BD Count Register (offset: 0x3C10)” on page 395 • “Send Max Coalesced BD Count Register (offset: 0x3C14)” on page 397 • “Status Block Host Address Register (offset: 0x3C38)” on page 400 Broadcom ® January 29, 2016 • 5718-PG108-R Page 4...
Page 5 • “04h: Auto_Negot_Advertisement_Register” on page 515 • “09h: 1000Base_T_Control_Register” on page 518 • “10h: PHY_Extended_Control_Register” on page 522 • “18h: Auxiliary Control Register (Shadow Register Selector = “000”)” on page 526 Broadcom ® January 29, 2016 • 5718-PG108-R Page 5...
Page 6 “B2HRX APE Broadcast Statistics Count (offset: 0x24F4)” on page 375 • “B2HRX APE Drop Packet Count (offset: 0x24F8)” on page 375 • “B2HRX APE Drop Packet Byte Count (offset: 0x24FC)” on page 375 Broadcom ® January 29, 2016 • 5718-PG108-R Page 6...
Page 7 “NVM Write Register (offset: 0x7008)” on page 497 Added: • “Device Closing Procedure” on page 147 • “TX TIME STAMP LSB REG (offset: 0x5C0)” on page 327 • “TX TIME STAMP MSB REG (offset: 0x5C4)” on page 327 Broadcom ® January 29, 2016 • 5718-PG108-R Page 7...
Page 8 “RMU Registers” on page 504 • “RMU_EGRESS_DA1_MATCH[1-8]_REG (offsets: 0x00B0, 0x00B8, 0x00C0, 0x00C8 … 0xE8)” on page 504 • “RMU_EGRESS_DA2_MATCH[1-8]_REG (Offsets 0x00B4, 0x00BC, 0x00C4, 0xCC …0xEC)” on page 504 • “RMU_EGRESS_STATUS_REG (Offset 0x0000)” on page 504 Broadcom ® January 29, 2016 • 5718-PG108-R Page 8...
Page 9 (offset: 0x3600)” on page 346. • Added BCM5719 to “Link Aware Power Mode Clock Policy Register (offset: 0x3610)” on page 349. • Added BCM5719 to “APE CLK Policy Register (offset: 0x361C)” on page 352. Broadcom ® January 29, 2016 • 5718-PG108-R Page 9...
Page 10 • “Global Mutex Grant Register (offset: 0x36F4)” on page 381 • “Temperature Monitor Control Register (offset: 0x36FC)” on page 382 • “BCM5719 Registers” on page 469 Removed: • “Reserved (offset: 0x378C)” Broadcom ® January 29, 2016 • 5718-PG108-R Page 10...
Page 11 Column from Table 1: “BCM5718 Family Product Features,” on page 40 • Register control mode from “MDI Register Access” on page 187 • MDI Control Register (offset: 0x6844) 5718-PG100-R 04/13/10 Initial release Broadcom ® January 29, 2016 • 5718-PG108-R Page 11...
Page 12: Table Of Contents
Write FIFO............................. 58 Buffer Manager............................59 LED Control..............................59 Memory Arbiter ............................59 Host Coalescing ............................60 Host Coalescing Engine ........................60 MSI FIFO............................... 61 Status Block ............................61 10BT/100BTx/1000BASE-T Transceiver ....................62 Broadcom ® January 29, 2016 • 5718-PG108-R Page 12...
Page 13 Single-Vector or INTx — RSS Mode Status Block Format ............. 84 Multivector RSS Mode Status Block Format .................. 85 Status Block and INT MailBox Addresses..................86 Section 5: Receive Data Flow................... 88 Introduction..............................88 Receive Producer Ring ..........................90 Broadcom ® January 29, 2016 • 5718-PG108-R Page 13...
Page 14 Section 6: Transmit Data Flow ..................105 Introduction............................... 105 Send Rings..............................105 Ring Control Block..........................107 Host-Based Send Ring........................108 Checksum Offload............................ 109 Large Segment Offload ..........................110 QuickStart............................110 LSO-Related Hardware Control Bits ....................111 Broadcom ® January 29, 2016 • 5718-PG108-R Page 14...
Page 15 Generating CRC..........................136 Checking CRC............................. 136 Initializing the MAC Hash Registers ....................136 Promiscuous Mode Setup/Configuration..................... 138 Broadcast Setup/Configuration ......................138 Section 7: Device Control ....................139 Initialization Procedure ..........................139 Broadcom ® January 29, 2016 • 5718-PG108-R Page 15...
Page 16 TX TIME WATCHDOG LSB[1] REG [Offset 0x6920]................166 TX TIME WATCHDOG MSB[1] REG [Offset 0x6924]................. 166 EAV REF-COUNT SNAP-SHOT LSB[1] REG [Offset 0X6930] ............166 EAV REF-COUNT SNAP-SHOT MSB[1] REG [Offset 0X6934] ............167 Broadcom ® January 29, 2016 • 5718-PG108-R Page 16...
Page 17 Power Supply in D3 State ........................191 Clock Control............................191 Device ACPI Transitions ........................192 Disable Device Through BIOS ......................192 Endian Control (Byte and Word Swapping) ................... 193 Background ............................193 Broadcom ® January 29, 2016 • 5718-PG108-R Page 17...
Page 18 Operational Characteristics ......................... 214 Internal Memory ........................... 214 WOL Pattern Configuration Register.................... 214 WOL Streams..........................215 Pattern Data Structure ......................... 217 Firmware Mailbox......................... 218 PHY Auto-Negotiation ........................219 Power Management ........................219 Broadcom ® January 29, 2016 • 5718-PG108-R Page 18...
Page 19 Single-Vector IOV Mode Status Block Format ................247 Multivector RSS Mode Status Block Format ................248 Multivector IOV Mode Status Block Format ................. 249 MSI-X Capability Structure ........................250 MSI-X Data Structures ........................251 Broadcom ® January 29, 2016 • 5718-PG108-R Page 19...
Page 20 MSI-X One Shot Mode ......................... 258 Coalesce Now or Forced Update ....................258 Misc Coalescing Controls......................258 Broadcom Tagged Status Mode (0x68[9]) ................258 Clear Interrupt, Mask Interrupt, Mask Mode (0x68[0], 0x68[1], 0x68[8]) ......259 Clear Ticks On Rx Bd Events Mode (0x3c00[9])..............259 No Interrupt On Force Update (0x3c00[11]).................
Page 21 UNDI Send BD Producer Index Mailbox Register (offset: 0x90–0x94) ..........287 UNDI Receive BD Standard Producer Ring Producer Index Mailbox Register (offset: 0x98–0x9C) .. 287 MSI-X Capabilities Registers....................... 288 MSI-X Capability Header Register (offset: 0xA0)................. 288 MSIX_TBL_OFF_BIR – 0xa4....................... 288 Broadcom ® January 29, 2016 • 5718-PG108-R Page 21...
Page 22 Register (offset: 0x260–0x264) ....................... 306 High Priority Mailbox Registers ......................307 Receive BD Standard Producer Ring Index Register (offset: 0x268-0x26F)......................307 Receive BD Jumbo Producer Ring Index Register (offset: 0x270) ..........307 Broadcom ® January 29, 2016 • 5718-PG108-R Page 22...
Page 23 Transmit MAC Lengths Register (offset: 0x464) ................. 321 Receive MAC Mode Register (offset: 0x468) ..................322 Receive MAC Status Register (offset: 0x46C) ..................324 MAC Hash Register 0 (offset: 0x470)....................324 Broadcom ® January 29, 2016 • 5718-PG108-R Page 23...
Page 24 Hash Key Register 9 (offset: 0x694) ....................337 Receive MAC Programmable IPv6 Extension Header Register (offset: 0x6A0) ......... 338 Statistics Registers ..........................339 Transmit MAC Static Counters......................339 ifHCOutOctets (offset: 0x800) ...................... 339 Broadcom ® January 29, 2016 • 5718-PG108-R Page 24...
Page 25 (offset: 0x8B8) ..................343 Ifnomorerxbd:0x224C........................343 Ifindiscard:0x2250 ........................343 Ifinerror:0x2254 ..........................343 APE_NETWORK_STATS_REGS (Offsets 0x900–0x9BC)..............344 Send Data Initiator Registers ........................345 Send Data Initiator Mode Register (offset: 0xC00)................345 Broadcom ® January 29, 2016 • 5718-PG108-R Page 25...
Page 26 Receive List Placement Statistics Increment Mask Register (offset: 0x201C)........360 Receive Selector List Head & Tail Pointers (offset: 0x2100)............... 360 Receive Selector List 1 Count Registers (Offset: 0x2108) ..............360 Receive Data and Receive BD Initiator Control Registers..............362 Broadcom ® January 29, 2016 • 5718-PG108-R Page 26...
Page 27 Receive BD Initiator Local NIC Jumbo Receive BD Producer Index (offset: 0x2C08) ......372 Receive BD Initiator Local NIC Receive BD Producer Index Register (offset: 0x2C0C–0x2C13) ..373 Standard Receive BD Producer Ring Replenish Threshold Register (offset: 0x2C18)....... 373 Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 28 Flash Clock Policy Register (offset: 0x366C) ..................399 Link Idle Control Register (offset: 0x3670) ..................401 Link Idle Status Register (offset: 0x3674) ................... 404 Top Level Miscellaneous Control 1 Register (offset: 0x367C) ............405 Broadcom ® January 29, 2016 • 5718-PG108-R Page 28...
Page 29 NIC Diagnostic Return Ring 2 Producer Index Register (offset: 0x3C88)........... 425 NIC Diagnostic Return Ring 3 Producer Index Register (offset: 0x3C8C) .......... 425 NIC Diagnostic Send BD Consumer Index Register (offset: 0x3CC0) ..........425 Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 30 Host Address for the DMA Read Channel 2 (offset: 0x4B38) ............. 446 Host Address for the DMA Read Channel 3 (offset: 0x4B40) ............. 447 Non-LSO Read DMA Reserved Control Register (offset: 0x4B74) ............. 447 Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 31 Flow Through Queues..........................463 FTQ Reset Register (offset: 0x5C00)....................464 MAC TX FIFO Enqueue Register (offset: 0x5CB8)................465 RXMBUF Cluster Free Enqueue Register (offset: 0x5CC8) ............... 465 RDIQ FTQ Write/Peak Register (offset: 0x5CFC)................465 Broadcom ® January 29, 2016 • 5718-PG108-R Page 31...
Page 32 TX Time Watchdog LSB[1] Reg (offset: 0x6920) ................. 484 TX Time Watchdog MSB[1] Reg (offset: 0x6924) ................ 485 EAV Ref Corrector Reg [Offset 0x6928) ..................485 EAV Ref Count Snapshot LSB[1] Reg (Offset 0x6930) ............... 485 Broadcom ® January 29, 2016 • 5718-PG108-R Page 32...
Page 33 0Fh: IEEE_Extended_Status_Register ....................506 10h–1Fh Register Map Detailed Description ..................508 10h: PHY_Extended_Control_Register....................508 11h: PHY_Extended_Status_Register (copper side only)..............509 12h: Receive_Error_Counter_Register ....................510 13h: False_Carrier_Sense_Counter_Register ..................511 14h: Local_Remote_Receiver_NOT_OK_Counters_Register ............511 Broadcom ® January 29, 2016 • 5718-PG108-R Page 33...
Page 34 1Dh: Master/Slave Seed Register (Bit 15 = 0) ..................543 1Dh: HCD Status Register (Bit 15 = 1)....................544 1Eh: Test1_Register..........................545 1Fh: Test2_Register..........................546 SerDes PHY Register Definitions......................547 Register Map ............................548 MII Control............................550 Broadcom ® January 29, 2016 • 5718-PG108-R Page 34...
Page 35 LPI Feature Enable ........................573 Appendix A: Flow Control ....................574 Notes................................574 Flow Control Scenario ..........................574 File Transfer ............................575 Speed Mismatch..........................575 Switch Buffers Run Low ........................576 Broadcom ® January 29, 2016 • 5718-PG108-R Page 35...
Page 36 BCM5717 / BCM5718 Memory Map ......................580 BCM5717 / BCM5718 Register Map......................583 BCM5719 Memory Map ..........................585 BCM5719 Register Map..........................587 BCM5720 Memory Map ..........................589 BCM5720 Register Map..........................590 Broadcom ® January 29, 2016 • 5718-PG108-R Page 36...
Page 37 Figure 31: Basic Driver Flow to Send a Packet ..................... 133 Figure 32: Local Contexts ..........................170 Figure 33: Header Type Register 0xE ......................171 Figure 34: Register Indirect Access ....................... 174 Figure 35: Indirect Memory Access ....................... 176 Broadcom ® January 29, 2016 • 5718-PG108-R Page 37...
Page 38 Figure 59: File Transfer Scenario: Switch Backpressure................577 Figure 60: File Transfer Scenario: Switch Flow Control................. 577 Figure 61: File Transfer Scenario: File Transfer Complete................578 Figure 62: Pause Control Frame........................578 Broadcom ® January 29, 2016 • 5718-PG108-R Page 38...
Page 39 Table 31: Receive BD Error Flags ......................... 119 Table 32: Receive BD Flags .......................... 120 Table 33: Receive BD Flags .......................... 122 Table 34: Send Buffer Descriptor Flags ......................123 Table 35: Status Block ........................... 124 Broadcom ® January 29, 2016 • 5718-PG108-R Page 39...
Page 40 Table 47: Device Specific Registers ......................172 Table 48: PCI Address Map Standard View ....................180 Table 49: GPIO Usage for Power Management for Broadcom Drivers ............191 Table 50: Ethernet Controller Power Pins...................... 191 Table 51: Endian Example..........................193 Table 52: Storage of Big-Endian Data ......................
Page 41 Table 104: Send BD Diagnostic Initiator ......................354 Table 105: Multiple Send Ring Mail Boxes ....................355 Table 106: BD Fetch Limit Register (Offset 0x2D08)..................375 Table 107: HC Parameter Set Reset Register (Offset: 0x3C28) ..............421 Broadcom ® January 29, 2016 • 5718-PG108-R Page 41...
Page 42 Table 138: 1000XSTATUS2 .......................... 561 Table 139: 1000XSTATUS3 .......................... 561 Table 140: FXCONTROL1..........................562 Table 141: FXCONTROL2..........................563 Table 142: FXCONTROL3..........................564 Table 143: FXSTATUS1 ..........................564 Table 144: ANALOG_TX1 ..........................565 Broadcom ® January 29, 2016 • 5718-PG108-R Page 42...
Page 43 Table 158: BCM5717 / BCM5718 Register Map.................... 583 Table 159: BCM5719 Memory Map ....................... 585 Table 160: BCM5719 Register Map....................... 587 Table 161: BCM5720 Memory Map ....................... 589 Table 162: BCM5720 Register Map....................... 590 Broadcom ® January 29, 2016 • 5718-PG108-R Page 43...
Page 44: About This Document
Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php. Document Conventions The following conventions may be used in this document:...
Page 45: References
Customer Support Portal (CSP) and Downloads & Support site (see Technical Support). For Broadcom documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name...
Page 46: Technical Support
Specification Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative.
Page 47: Section 1: Introduction
Tx/Rx over IPv4/IPv6 IP checksum offload on Tx/Rx over IPv4/IPv6 Hardware TCP segmentation offload over IPv4/IPv6 Jumbo frame support Receive-side scaling (RSS) UDP Receive-side scaling (UDP RSS) No Transmit-side scaling (TSS) Broadcom ® January 29, 2016 • 5718-PG108-R Page 47...
Page 48 Interface to Flash memory Interface to Serial EEPROM Flash Autoconfig Support Self-Test Test modes (BIST, SCAN, etc) JTAG support Technology High-performance, low-overhead software/hardware interface High-speed on-chip RISC processors (one per port) Broadcom ® January 29, 2016 • 5718-PG108-R Page 48...
Page 49: Revision Levels
PCI Revision ID and Chip ID information in the PCI configuration registers to determine the revision level of the Ethernet controller on the board, and then load the appropriate workaround described in the errata sheets. The Broadcom PCI vendor ID is 0x14E4. Table 3 shows the default values of PCI device IDs.
Page 50: Programming The Ethernet Controllers
“Revision Levels” on page 49) that provide the necessary information for writing a host- ® based device driver. The Broadcom Linux driver (a.k.a. “tg3”) is also a very good reference source for writing your own driver. The programming model for the NetXtreme/NetLink Ethernet controllers does not depend on OS or processor ®...
Page 51: Section 2: Hardware Architecture
Processor Write Write Applications FIFO Processing Boot ROM Engine (APE runs Ring Controllers firmware such Host Coalescing as NC-SI) Queue Management LED Control EEPROM Control NVRAM 125-MHz Clock LED Signals Interface Broadcom ® January 29, 2016 • 5718-PG108-R Page 51...
Page 52: Overview Of Features
Overview of Features Overview of Features The BCM5718 family of controllers represents the third generation of Broadcom NetXtreme multi-port Gigabit Ethernet controllers. This family is the successor to the BCM5714/BCM5715 family. The BCM5717, BCM5718, and BCM5720 feature two independent 1 Gb Ethernet ports on the network side. A host computer can communicate with the controller over a single PCIe link.
Page 53: Figure 2: High-Level System Functional Block Diagram
GHPY 0 Serdes 0 GHPY 1 Serdes 1 Port 1 Port 0 Note: BCM5719 has the same general architecture, but four ports (ports 0, 1, 2, 3) and a quad-function PCIe interface. Broadcom ® January 29, 2016 • 5718-PG108-R Page 53...
Page 54: Receive Data Path
The RX FIFO provides elasticity while data is read from PHY transceiver and written into internal memory. There are no programmable settings for the RX FIFO. This FIFO’s operation is completely transparent to host software. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 55: Rules Checker
DMA of one or more new BDs to the NIC. The actual DMAs generated depend on the comparison of the value of the received BD host producer index mailbox, the NIC copy of the received BD consumer index, and the local copy of the received BD producer index. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 56: Transmit Data Path
The TX FIFO provides elasticity while data is moved from device internal memory to PHY. There are no programmable settings for the TX FIFO. This FIFO’s operation is completely transparent to host software. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 57: Dma Read
The Read DMA engine makes sure there is enough space in internal Tx Packet Buffer Memory before initiating a DMA request for transfer of Tx packet data from host memory to device internal packet memory. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 58: Buffer Manager
This reduces latency on the PCI bus during the write operation (wait states are not inserted while data is fetched from internal memory). The operation of the write DMA FIFO is transparent to host software. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 59: Buffer Manager
The MA negotiates local memory access, so all portions of the architecture are provided with fair access to memory resources. The MA prevents starvation and bounds access latency. Host software may enable/disable/ reset the MA, and there are no tunable parameters. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 60: Host Coalescing
Status Buffer Write Write Memory Manager FIFO Engine PCIe Interface Tick Counter Counter MSI Mailbox FIFO Host Coalescing Engine Host Interrupt Driver Controller Host software may configure line IRQ or MSI Broadcom ® January 29, 2016 • 5718-PG108-R Page 60...
Page 61: Msi Fifo
DMA write engine, so host software gets a refreshed copy of status. The status block is refreshed before a line IRQ or MSI is generated. See “Status Block Format” on page 82 for a complete discussion of the status block. Broadcom ® January 29, 2016 • 5718-PG108-R Page 61...
Page 62: 10Bt/100Btx/1000Base-T Transceiver
The MII is used in conjunction with 10/100 Mbps copper Ethernet transceivers. • GMII supports 1000 Mbps copper Ethernet transceivers. MII Block The MII interconnects the MAC and PHY sublayers (as shown in Figure 8 on page 63). Broadcom ® January 29, 2016 • 5718-PG108-R Page 62...
Page 63: Figure 8: Media Independent Interface
Decoder Media Status LNKRDY Control TXD /4 MII_TXCLK Symbol Media Tx Data Encoder TX_ER Access Encapsulation Mgmnt TX_EN 2.5 MHz at 10 Mbps 4-bit Data Path 25 MHz at 100 Mbps Broadcom ® January 29, 2016 • 5718-PG108-R Page 63...
Page 64: Gmii Block
The PHY will drive Carrier Sense (CRS) as a response to traffic being sent/received. The MAC sublayer can monitor traffic and subsequently drive traffic LEDs. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 65: Figure 9: Gmii Block
Access Decapsulation RX_ER Mgmnt Symbol RX_DV Decoder Media Status LNKRDY Control TXD /8 TX Media TX_CLK0 Symbol Tx Data Access Encoder TX_ER Encapsulation Mgmnt TX_EN 125-MHz Ref Clock 8-bit Data Path Broadcom ® January 29, 2016 • 5718-PG108-R Page 65...
Page 66: Mdio Register Interface
PHY transfers status back to the MAC, using MDIO. Management Data Interrupt The integrated Broadcom PHY may be programmed to generate interrupts. A PHY status change initiates a Management Data Interrupt (MDINT). A MDI mask register allows host software to selectively enable/disable status types, which cause MDINT notification.
Page 67: Section 3: Nvram Configuration
All configuration settings are default-configured in the official release binary image files provided in Broadcom's CD software releases. However, the settings chosen as default by Broadcom may not be what best suits a particular OEM's application, so some settings may need to be changed by the OEM.
Page 68: Self-Boot
Details relating to self-boot can be found in Self Boot Option (5754X_5787X-AN10X-R) and NetXtreme/NetLink Software Self-Boot NVRAM (NetXtreme-AN40X-R) Broadcom application notes. Broadcom ®...
Page 69: Section 4: Common Data Structures
There are three main types of descriptor rings: • Send Rings • Receive Producer Rings • Receive Return Rings The TX/RX ring base requires an 8 byte alignment. The receive buffer address (recorded in SBD/RBD) cannot cross 4G. Broadcom ® January 29, 2016 • 5718-PG108-R Page 69...
Page 70: Producer And Consumer Indices
Cons The delta between the producer and consumer indices is indicated by the shaded areas. These shaded descriptors are considered to be valid (non-empty) and thus need to be processed. Prod Broadcom ® January 29, 2016 • 5718-PG108-R Page 70...
Page 71: Ring Control Blocks
Ring is provided in “PCI” on page 168. Send Ring Control Blocks The format of the Send RCB remains unchanged, only 15 more are added as shown in the Table below. Broadcom ® January 29, 2016 • 5718-PG108-R Page 71...
Page 72: Receive Ring Control Blocks
Max Length/Flag 0x2458 0x2448 0x208 NIC Address 0x245C 0x244C 0x20C Host Address High 0x2510 0x2500 0x210 Host Address Low 0x2514 0x2504 0x214 Max Length/Flag 0x2518 0x2508 0x218 NIC Address 0x251C 0x250C 0x21C Broadcom ® January 29, 2016 • 5718-PG108-R Page 72...
Page 73: Send Rings
A single transmit packet may be composed of multiple buffers that are pointed to by multiple send descriptors. The maximum number of send descriptors for a single packet is (0.75)*(ring size). Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 74: Figure 12: Transmit Ring Data Structure Architecture Diagram
RX/TX max coalesced frames RX Prod #3 thresholds are met. Software can RX Prod #4 examine the TX consumer indices in the status block to determine which packets have been sent by the hardware. Broadcom ® January 29, 2016 • 5718-PG108-R Page 74...
Page 75: Send Buffer Descriptors
If this bit is set to 0, then the Consumer Index is only updated as soon as one of the host interrupt coalescing conditions has been met. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 76: Large Segment Offload (Lso) Send Bd
If VLAN tag insertion is desired, this field (and the flag) should be set in the first descriptor for that packet (i.e., the descriptor that points to the buffer that contains the Ethernet header). Large Segment Offload (LSO) Send BD “Large Segment Offload” on page 110. Broadcom ® January 29, 2016 • 5718-PG108-R Page 76...
Page 77: Receive Rings
After the controller fetches and caches (e.g., consumes) this receive producer descriptor, the controller will update the consumer index of the receive producer ring. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 78: Receive Return Rings
Once a packet has been received, the controller will modify this length field to correspond to the length of the packet received. A value of 0 indicates that there is no valid data in the buffer. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 79: Table 12: Defined Flags For Receive Buffers
If set to 1, indicates host that the RSS_Hash in Receive BD of return ring is valid. PACKET_END If set to 1, the packet ends with the data in the buffer pointed to by this descriptor. Reserved Should be set to 0. Broadcom ® January 29, 2016 • 5718-PG108-R Page 79...
Page 80: Table 13: Defined Error Flags For Receive Buffers
IP_CHECKSUM (Flags bit 12) to determine if the IP checksum in the received packet is correct. This field used to contain the actual IP checksum value but that is not true for the BCM5718 family of controllers. Only the Flags bit IP_CHECKSUM should be relied on by host driver software as is done by Broadcom drivers.
Page 81: Additional Ring Information For The Bcm5718 Family
Send ring as non-jumbos. There are no separate jumbo-dedicated Send ring(s) like there are for Rx producer rings. The max sizes of the various rings is as follow: • Rx Ret: 4096 • Rx Prod: 2048 Broadcom ® January 29, 2016 • 5718-PG108-R Page 81...
Page 82: Status Block
Each MSI-X vector is associated with a status-block structure. A status block is DMAed to the host memory immediately prior to raising a legacy style interrupt (INTx, MSI) or MSI-X interrupt. Status block formats vary depending on RSS and the MSI-X vector number. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 83: Intx/Msi - Legacy Mode Status Block Format
Receive Jumbo Producer Ring Consumer Index Status-Block [0] Status Word Format (single-vector RSS): • Bit [0]: Update bit • Bit [1]: Link status change • Bit [2]: Error/attention • Bits [31:3]: Reserved 0x0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 83...
Page 84: Single-Vector Or Intx - Rss Mode Status Block Format
Receive Jumbo Producer Ring Consumer Index Status-Block [0] Status Word Format (single-vector RSS): • Bit [0]: Update bit • Bit [1]: Link status change • Bit [2]: Error/attention • Bits [31:3]: Reserved — always 0x0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 84...
Page 85: Multivector Rss Mode Status Block Format
Valid only for Status Block4 else RSVD 0x0 0x10 Reserved 0x0 Receive Return Ring 0 Producer Index Valid only for Status Block1 else RSVD 0x0 0x14 Reserved 0x0 Reserved 0x0 Status-Block [1–4] Status Word Format (multivector RSS): Broadcom ® January 29, 2016 • 5718-PG108-R Page 85...
Page 86: Status Block And Int Mailbox Addresses
This provides the host driver with a mechanism to determine whether the status block has been updated since the last time the driver looked at the status block. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 87 Send Ring Consumer Index. This provides the host software with an indication that the controller has buffered this send data and, therefore, the host software may free the buffer that was just consumed by the device. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 88: Section 5: Receive Data Flow
Returned BD in Return Ring. The device driver will then reinitialize the identified BD in Producer Ring with a new allocated buffer and replenish the Receive Producer Ring with this BD. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 89: Figure 14: Receive Buffer Descriptor Cycle
Protocol Interface List Local Rx MAC Coalescing Service (i.e. TCP/IP) Initiator Memory Engine Routine DMA Write Engine RX Indicate Available Return Ring 1 Return Ring 2 Return Ring 3 Return Ring 4 Broadcom ® January 29, 2016 • 5718-PG108-R Page 89...
Page 90: Receive Producer Ring
322). If the Accept Oversized bit (bit 5) of this register is set, the Ethernet controller accepts packets (of size up to 64 KB) larger than the size specified in the MTU. Broadcom ® January 29, 2016 • 5718-PG108-R Page 90...
Page 91: Rcb Setup Pseudo Code
There are no requirements for memory alignment or cache line integrity for the Ethernet controller. Unlike send buffer descriptors, the receive buffer descriptors cannot be chained to support multiple fragments. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 92: Management Of Rx Producer Rings With Mailbox Registers And Status Block
Indirect Mode) Register Access 0x200–0x207 0x5800–0x5807 Interrupt Mailbox 0 0x208–0x20F 0x5808–0x580F Interrupt Mailbox 1 0x268–0x26F 0x5868–0x586F Receive BD Standard Producer Ring Producer Index 0x280–0x287 0x5880–0x5887 Receive BD Return Ring 1 Consumer Index Broadcom ® January 29, 2016 • 5718-PG108-R Page 92...
Page 93: Receive Return Rings
The RCB max_len field is used to indicate the number of buffer descriptor entries in a return ring. If an invalid value is set, the Ethernet controller indicates an attention error in the Flow Attention register. Figure 13 on page 77 shows receive return rings. Broadcom ® January 29, 2016 • 5718-PG108-R Page 93...
Page 94: Management Of Return Rings With Mailbox Registers And Status Block
There are two crucial items: • The use of non-cached and physically contiguous memory is best for adapter performance. • Physical memory mapping is required for the controller’s internal copies of logical host memory. Broadcom ® January 29, 2016 • 5718-PG108-R Page 94...
Page 95: Receive Rules Setup And Frame Classification
1 if the rules are not being used to ensure that all received packets will be DMAed to return ring 1. Table 21: Receive Rules Configuration Register Bits Field Access 31:8 Reserved Specifies the default class (ring) if no rules are matched Reserved Broadcom ® January 29, 2016 • 5718-PG108-R Page 95...
Page 96: Receive List Placement Rules Array
Must be set to zero. 17:16 Comparison Operator specifies how to determine the match: – • 00 = Equal • 01 = Not Equal • 10 = Greater than • 11 = Less Than Broadcom ® January 29, 2016 • 5718-PG108-R Page 96...
Page 97: Class Of Service Example
Example: If you wanted to set a Class of Service (CoS) of 2 based on the eighth byte in the data portion of an encapsulated IPX frame using Ethernet Type 2 having a value greater than 6, you could set up the rules shown in Figure 16 on page Broadcom ® January 29, 2016 • 5718-PG108-R Page 97...
Page 98: Checksum Calculation
In the Receive MAC Mode register (offset 0x468–0x46b), the Keep VLAN Tag Diag Mode bit (bit 10) can be set to force the Ethernet controller to not strip the VLAN tag from the packet. This is only for diagnostic purposes. Broadcom ®...
Page 99: Table 25: Frame Format With 802.1Q Vlan Tag Inserted
MAC source address 12:13 Tag Protocol ID (TPID)—0x8100 14:15 Tag Control Information (TCI): • Bit 15:13—IEEE 802.1P priority • Bit 12—CFI bit • Bit 11:0—VLAN ID 16:17 The original EtherType 18:1517 Payload Broadcom ® January 29, 2016 • 5718-PG108-R Page 99...
Page 100: Rx Data Flow Diagram
4. A valid Ethernet packet is received from the network into the device. 5. The Ethernet packet is DMAed to host memory using a BD previously DMAed from a Receive Producer Ring. Broadcom ® January 29, 2016 • 5718-PG108-R Page 100...
Page 101: Receive Side Scaling
Hash result to determine which of the n CPUs are processing the packet, where n is the number of CPUs assigned to process received packets. • Adds a Base CPU Number to determine the exact CPU that will process the packet. Broadcom ® January 29, 2016 • 5718-PG108-R Page 101...
Page 102: Rss Parameters
The RSS Hash Mask bits (bits 22:20 of the Receive MAC Mode register at offset 0x468) allow the configuration of number of hash-result bits that are used to index into the indirection table. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 103: Indirection Table
(while the current receive descriptor queues are being processed) for packets to be processed on the wrong CPU. This is a normal transient condition and should not be a problem. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 104: Rss Rx Packet Flow
6. Each CPU processes the new RBDs in it’s receive return ring when its packet handler routine is started by main ISR. 7. Once the main ISR determines that all new RBDs have been processed by the CPUs, it enables the interrupts from the device and exits. Broadcom ® January 29, 2016 • 5718-PG108-R Page 104...
Page 105: Section 6: Transmit Data Flow
As a descriptor is processed, the consumer index is incremented, and the new index is reflected in a new status block update. Status block is described in “Status Block” on page Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 106: Figure 19: Relationships Between All Components Of A Send Ring
Send BD 1 Buffer Send BD 2 Send Send BD 3 Send BD 4 Buffer Send BD 5 Send BD 6 Send BD 7 Buffer Consumer Send BD 8 Producer Send BD 512 Broadcom ® January 29, 2016 • 5718-PG108-R Page 106...
Page 107: Ring Control Block
Figure 20: Max_Len Field in Ring Control Block 1st Ring Element 512th Ring Element Host Send Ring Control Block Offset 0x00 Host Ring Address 0x04 Flags 0x08 Max_Len NIC Ring Address 0x0C Broadcom ® January 29, 2016 • 5718-PG108-R Page 107...
Page 108: Host-Based Send Ring
The host software uses the send ring consumer index and its producer index to determine the empty slots in the ring. The Ethernet controller implements an algorithm that periodically DMAs the status block to host memory in an efficient manner. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 109: Checksum Offload
Note: In LSO enabled case, a driver needs to zero the TCP checksum field coming from upper layer of OS when doing TX CSO. Also, make sure to set bit-27 and bit-28 of 0x4800 when doing TX CSO in both LSO/Non LSO mode. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 110: Large Segment Offload
This significantly reduces the work done by the host CPU. Some Broadcom Ethernet controllers, such as the BCM5718, also support using jumbo sized frames (up to 9,216 bytes) as the individual frame size into which a large offloaded TCP packet is segmented into.
Page 111: Lso-Related Hardware Control Bits
BCM5718 Programmer’s Guide Large Segment Offload Note: In Broadcom controllers that have a physically separate isochronous (ISO) TX queue, there is a parallel set of register fields, which mirror that of the normal TX path, for controlling LSO on the ISO TX path.
Page 112: Send Buffer Descriptor
TX packets onto the wire. Note: LSO using jumbo frames is permissible on some Broadcom controllers (i.e., BCM5718). This is accomplished by appropriately programming the MSS field of the Send BD.
Page 113: Mss[13:0]
DMA'd to the host as soon as this buffer's data has been DMA'd from the host. An interrupt may or may not be generated depending on the present state of interrupt avoidance mechanisms. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 114: Lso Limitations
The TCP/UDP and IP checksum offload enable bits in the SBD may be either set or cleared. The hardware still works as expected when LSO is in use (i.e., checksums are calculated/inserted by the hardware since this is a natural requirement for doing LSO). Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 115: Example Tcp-Segmentation-Related (Lso) Register Values
The driver should zero the TCP checksum field in the offloaded TCP packet, but leave the IP checksum alone. This requirement may change with newer NetXtreme controllers. Broadcom drivers enable long burst by default in the Read DMA Mode register (0x4800 bits 17:16 = 11 binary = 4k byte burst size).
Page 116: Jumbo Frames
The receive side retrieves buffers only from the jumbo producer ring in turn to post a received jumbo frame. Similarly, the receive side only retrieves buffers from the standard producer ring in turn to post standard sized frames. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 117: Affected Data Structures
118. The main distinction of the extended BD structure is that it can point to a maximum of four pieces of a scattered receive buffer. Hence the structure contains four host addresses and four length fields. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 118: Figure 23: Extended Rx Buffer Descriptor
Note: Len 0 is not permitted to be 0. Len1, Len2, or Len 3 may be set to 0, but hardware ignores Len2 and Len3 when Len1 = 0. Similarly, hardware ignores Len4 when Len3 = 0. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 119: Table 31: Receive Bd Error Flags
This field used to contain the actual IP checksum value, but that is not true for the BCM5718 Family of controllers. Only the Flags bit IP_CHECKSUM should be relied on by host driver software as is done by Broadcom drivers. •...
Page 120: Receive Jumbo Producer Ring
The controller keeps a local copy of the jumbo ring consumer index in register 0x2470. The jumbo ring consumer index is also reported to the host via the status block. See “Send Buffer Descriptor” on page 122). Broadcom ® January 29, 2016 • 5718-PG108-R Page 120...
Page 121: Ring Control Blocks
Receive jumbo producer ring: Max Len should be programmed by the host to indicate the maximum number of entries the ring will hold. The allowable values for the jumbo producer ring Max Len are 32, 64, 128, 256, 512, and 1024. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 122: Receive Return Ring(S)
Send Buffer Descriptor The send buffer descriptor (SBD) has been updated to accommodate LSO over jumbo frames. Figure 25 on page 123 below illustrates the updated SBD format. Broadcom ® January 29, 2016 • 5718-PG108-R Page 122...
Page 123: Figure 25: Send Buffer Descriptor
Alternately, if hardware LSO is enabled and this bit is set in conjunction with CPU post-DMA, then this buffer is treated as part of an LSO segment to be further segmented by hardware. Broadcom ® January 29, 2016 • 5718-PG108-R Page 123...
Page 124: Status Block
Receive Return Ring 2 Producer Index Receive Return Ring 3 Producer Index 0x10 Send BD Consumer Index Receive Return Ring 0 Producer Index 0x14 Reserved 0x0 Receive Jumbo Producer Ring Consumer Index Broadcom ® January 29, 2016 • 5718-PG108-R Page 124...
Page 125: Misc Bd Memory
DMAed to the host by the controller. A conceptual diagram of the Send Interface is shown in Figure 26 on page 126 below. Broadcom ® January 29, 2016 • 5718-PG108-R Page 125...
Page 126: Receive Interface
(but <= Max Frame Size) arrives, the controller attempts to place the frame in such a buffer and ends up truncating the frame. • RX frames larger than Max Frame Size are placed in buffers retrieved from the RX jumbo producer ring. Broadcom ® January 29, 2016 • 5718-PG108-R Page 126...
Page 127: Figure 27: Receive Producer Interface
The consumption of receive return packets by the driver is communicated to the controller via the receive return consumer ring index mailbox register. A conceptual diagram of the Receive Return Interface is shown in Figure 28 on page 128 below. Broadcom ® January 29, 2016 • 5718-PG108-R Page 127...
Page 128: Large Segment Offload (Lso/Tso)
MBUFs worth of packet header data. 1st Mbuf gives: 128, Mbuf-header (8B), Frame Header field (40B) = 80B; 2nd Mbuf gives: 128, Mbuf Header (8B) = 120B. Hence the total space for all headers, which includes all L2/L3/L4 combined, and options cannot exceed 200 bytes. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 129: Summary Of Register Settings To Support Jumbo Frames
Standard replenish threshold register 0x2C18 is typically 1/8 of total receive BDs in host memory. Jumbo replenish threshold register 0x2C1C is typically 1/8 of total Receive BDs in host memory. • EMAC MTU register 0x43C: Program this register based on max packet size. Broadcom ® January 29, 2016 • 5718-PG108-R Page 129...
Page 130: Scatter/Gather
SendBd1 through SendBd5. These buffer descriptors must be initialized in the send ring in a consecutive order, SendBd1 to SendBd5. The last send buffer descriptor of a frame must have the PACKET_END bit of Send BD Flags field set to indicate the end of a frame. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 131: Vlan Tag Insertion
“Status Block” on page 82). 7. The status block is DMAed to host memory. This DMA is subject to host coalescing, and the NIC may generate an interrupt at this point. Broadcom ® January 29, 2016 • 5718-PG108-R Page 131...
Page 132: Figure 30: Transmit Data Flow
NIC Memory Send Consumer Index Send BD 1 Status Block Send Producer Send BD n Index Send BD n+1 Send BD n+2 Buffer 1 SendBD 128 Buffer 2 Info Buffer 3 Broadcom ® January 29, 2016 • 5718-PG108-R Page 132...
Page 133: Figure 31: Basic Driver Flow To Send A Packet
Is this the last virtual buffer for this packet? Set BD_FLAG_END bit in send BD Update the Send Producer Index. This tells the HW that a new packet is ready to be transmitted Broadcom ® January 29, 2016 • 5718-PG108-R Page 133...
Page 134: Reset
However, there may still be a very small external NVRAM device which may contain some configuration items and possibly boot code “patches” to be applied to the ROM'd self-boot, boot code. Refer to the following Broadcom Application Notes for additional self-boot and general NVRAM access information: •...
Page 135: Mac Address Setup/Configuration
Ethernet controller. Since there are 128 hash table entries, 7 bits are used from the CRC. When hash table is extended to 256 entries, 8 bits from the CRC will be used as hash index. The MAC hash registers are ignored if the receive MAC is in promiscuous mode. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 136: Ethernet Crc Calculation
0x0470 and the least significant 32-bit resides in Mac_Hash_Register_3 at offset 0x047c. Host software can enable the reception of all multicast frames including broadcast frames by setting all four multicast hash registers to 0xFFFFFFFF. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 137: Table 37: Multicast Hash Table Registers
BufferSize) // Size of the buffer. unsigned long Reg; unsigned long Tmp; unsigned long j, k; Reg = 0xffffffff; for(j = 0; j < BufferSize; j++) Reg ^= pBuffer[j]; Broadcom ® January 29, 2016 • 5718-PG108-R Page 137...
Page 138: Promiscuous Mode Setup/Configuration
The following is a sample of the two receive rules for discarding broadcast frames. Rule1 Control: 0xc2000000 Rule1 Mask/Value: 0xffffffff Rule2 Control: 0x86000004 Rule2 Mask/Value: 0xffffffff Broadcom ® January 29, 2016 • 5718-PG108-R Page 138...
Page 139: Section 7: Device Control
9. Now that the Indicate Driver is ready to receive traffic, set the Host_Stack_Up bit in the General Mode Control register (see “Mode Control Register (offset: 0x6800)” on page 468). 10. Configure TCP/UDP pseudo header checksum offloading. Broadcom ® January 29, 2016 • 5718-PG108-R Page 139...
Page 140: Table 38: Recommended Bcm57Xx Ethernet Controller Memory Pool Watermark Settings
430, and “Read DMA MBUF High Watermark Register (offset: 0x4418)” on page 430). Broadcom has run hardware simulations on the Mbuf usage and strongly recommends the settings shown in Table These settings/values establish proper operation for 10/100/1000 speeds.
Page 141 24. Configure random backoff seed for transmit. See the Ethernet Transmit Random Backoff register (see “Ethernet Transmit Random Backoff Register (offset: 0x438)” on page 316). Broadcom recommends using the following algorithm: Seed = (MAC_ADDR[0] + MAC_ADDR[1] + MAC_ADDR[2] + MAC_ADDR[3] + MAC_ADDR[4] + MAC_ADDR[5]) &...
Page 142 • Sixteen active lists • One bad frames class 29. Write the Receive List Placement Statistics mask. Broadcom drivers write a value of 0x7BFFFF (24 bits) to the Receive List Placement Stats Enable Mask register (see “Receive List Placement Statistics Enable Mask Register (offset: 0x2018)”...
Page 143: Table 40: Recommended Bcm57Xx Ethernet Controller Host Coalescing Tick Counter Settings
Ticks Register (offset: 0x3C08)” on page 414” “Send Coalescing Ticks Register (offset: 0x3C0C)” on page 415). The clock begins ticking after RX/TX activity. Broadcom recommends the settings shown inTable Table 40: Recommended BCM57XX Ethernet Controller Host Coalescing Tick Counter Settings...
Page 144 52. Delay 40 microseconds. 53. Set 0x4800[24] = 0 to Allows multiple outstanding read requests from the non-LSO read DMA engine. 54. Set 0x4800[17:16] = 11b to Allows 4KB burst length reads for Jumbo/LSO network frames. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 145 • Various Hash Enable bits–if using RSS mode (Receive Side Scaling) 66. Delay 10 microseconds. 67. Setup the LED Control Register (0x40C). The Broadcom driver uses a value of 0x800 when initializing this register. 68. Activate link and enable MAC functional blocks by setting the Link_Status bit in the MI Status register (see “MII Status Register (offset: 0x450)”...
Page 146: Device Reset Procedure
8. Enable the MAC memory arbiter by setting the Enable bit in the Memory Arbiter Mode register (see “Memory Arbiter Mode Register (offset: 0x4000)” on page 426). 9. Initialize the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (offset: 0x68)” on page 282). Broadcom ® January 29, 2016 • 5718-PG108-R Page 146...
Page 147: Device Closing Procedure
4. Disable all the transmit blocks. a. Clear the Enable bit in the Send BD Selector Mode register (offset: 0x1400) b. Clear the Enable bit in the Send BD Initiator Mode Register (offset: 0x1800) Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 148: Energy Efficient Ethernet
// Setup PHY DSP for EEE mii_write(0x18, 0x0C00); mii_write(0x17, 0x4022); mii_write(0x15, 0x017B); mii_write(0x18, 0x0400); if (enable EEE advertisement) // Enable EEE advertisement for 100Base-TX and 1000Base-T modes mii_write(0x0D, 0x0007); mii_write(0x0E, 0x003C); mii_write(0x0D, 0x4007); Broadcom ® January 29, 2016 • 5718-PG108-R Page 148...
Page 149 // Set EEE LPI exit timing for 100mb link speed reg_write(0x36d0, 0x384); //delay 1000 milliseconds ms_delay(1000); // Read PHY’s EEE negotiation status mii_write(0x0d, 7); mii_write(0x0e, 0x803e); mii_write(0x0d, 0x4007); val = mii_read(0x0e); Broadcom ® January 29, 2016 • 5718-PG108-R Page 149...
Page 150 ((mii_read(0x19) & 0x500) == 0x500) //link negotiated to 100Mbps reg_write(0x36d0, 0x384); ms_delay(1000);//delay 1000 milliseconds //Assert LPI reg_write(0x36b0,(reg_read(0x36b0) | 0x80)) break; else ms_delay(500);//delay 500 milliseconds i++; if (i >= 100) Link_not_detected(); Broadcom ® January 29, 2016 • 5718-PG108-R Page 150...
Page 151 ™ BCM5718 Programmer’s Guide Energy Efficient Ethernet Broadcom ® January 29, 2016 • 5718-PG108-R Page 151...
Page 152: Section 8: Ieee1588
Transmit IP, UDP, TCP checksum offload – IP/UDP Transmit Checksum offload is applicable to UDP PTP packets, provided the packets are appropriately formatted by the software protocol engine, that is, 2B UDP padding etc must be taken care by software. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 153: Ptp Link Delay Measurement
Assume that both nodes contain a NetXtreme Time-Synch Capable NIC. Table 44 on page 154 describes the roles the PTP software component and Time-Synch capable NIC hardware play during above exchange. Broadcom ® January 29, 2016 • 5718-PG108-R Page 153...
Page 154: Hardware Description
A 64-bit RX Time Stamp Register + A 16-bit RX PTP Sequence ID Register • An RX Time Stamp Lock Timer Each of above items is described separately in the following sections. Broadcom ® January 29, 2016 • 5718-PG108-R Page 154...
Page 155: Eav Reference Clock/Counter
3. The driver may read the value of the free-running counter anytime. For that purpose, a 32-bit Register pair is provided. 4. The driver may take a snap-shot of this counter. Broadcom ® January 29, 2016 • 5718-PG108-R Page 155...
Page 156: Eav Reference Corrector
EAV Reference clock, although there could be a < 5ns routing delay present. A register is available in the CPMU block in which the clock-divisor value may be programmed by host software. The available output frequency range is 125 MHz through 4.8 MHz. See the Flash Clock Policy Register (0x366C). Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 157: Transmit Time Stamping Service
When this bit is set, the NIC will insert a VLAN tag in the Ethernet header. The value for the inserted tag is taken from the VLAN Tag field in the send BD. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 158: Receive Time Stamp And Sequence Id Registers
The frame ends at the end of the data in this buffer descriptor. RSS_HASH_VALID If this bit is 1, then the RSS_HASH_TYPE field is valid. Else the RSS_HASH_TYPE field is meaningless and must be ignored for this frame. Broadcom ® January 29, 2016 • 5718-PG108-R Page 158...
Page 159 Indicates that the IP Checksum field is valid. TCP_UDP_CHECKSUM Indicates that the TCP_UDP_Checksum field is valid. TCP_UDP_IS_TCP Indicates that this frame has a TCP packet in it. IPV6_PACKET Indicates that this frame has an IPv6 packet in it. Broadcom ® January 29, 2016 • 5718-PG108-R Page 159...
Page 160: Time Sync Registers
Writing to this MSB transfers the 64-bit value, this plus previously latched LSB, to EAV Ref Counter and counting immediately resumes from there. Back to back writes to this MSB has no effect. Broadcom ® January 29, 2016 • 5718-PG108-R Page 160...
Page 161: Eav Ref Clock Control Reg [Offset 0X6908]
Up -> Down Reset on GRC Reset and Reset on GRC Reset pulse PCIe FLR Reset on PCIe reset Reset on de-asserting edge of PCIe Reset Reserved Resume EAV Ref Count 2 Broadcom ® January 29, 2016 • 5718-PG108-R Page 161...
Page 162: Eav Ref-Count Snap-Shot Lsb[0] Reg [Offset 0X6910]
Read-LSB followed by Read-MSB. Once the LSB is read, the pair attains a frozen state, and is unfrozen immediately after a subsequent MSB read – if another TX packet passes to the wire between these two reads, it’s time stamp capture request is ignored by hardware. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 163: Tx Time Stamp Msb Reg [Offset 0X05C4]
INTERLOCK POLICY] field. RX Time Stamp [Upper 30:0 MSB of the RX Time Stamp. half] RX PTP SEQUENCE ID REG [Offset 0X06B8] Name Bits Access Default Value Description Reserved 31:16 RO 0x0000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 163...
Page 164: Rx Lock Timer Lsb Reg [Offset 0X06C0]
Lock Timer has expired. 11 => Reserved Note: Changing the state of this field while receiving PTP traffic may result in abrupt HW behavior. This field is best configured statically. Broadcom ® January 29, 2016 • 5718-PG108-R Page 164...
Page 165: Tx Time Watchdog Lsb[0] Reg [Offset 0X6918]
31:0 0x0000 See TX Time Watchdog MSB[0] Register. TX TIME WATCHDOG MSB[0] REG [Offset 0x691C] Name Bits Access Default Value Description Enable Lock Timer Write a 1 to enable Time Watchdog[0]. Broadcom ® January 29, 2016 • 5718-PG108-R Page 165...
Page 166: Tx Time Watchdog Lsb[1] Reg [Offset 0X6920]
APE_GPIO pin – a toggle serves a trigger. The only legal sequence of accessing this pair is Read-LSB followed by Read-MSB. Name Bits Access Default Value Description EAV Reference Count 31:0 LSB of the EAV Reference Count as snapshotted by Snap-shot [lower half] TimeSync/APE_GPIO [2:0] shall always be 000. Broadcom ® January 29, 2016 • 5718-PG108-R Page 166...
Page 167: Eav Ref-Count Snap-Shot Msb[1] Reg [Offset 0X6934]
Time Sync Registers EAV REF-COUNT SNAP-SHOT MSB[1] REG [Offset 0X6934] Name Bits Access Default Value Description EAV Reference Count 31:0 MSB of the EAV Reference Count as snapshotted by Snap-shot [Upper half] TimeSync/APE_GPIO. Broadcom ® January 29, 2016 • 5718-PG108-R Page 167...
Page 168: Section 9: Pci
PCI indirect mode for memory, registers, and mailboxes access. A specific example of a device driver, which uses indirect mode, is the Preboot Execution (PXE) driver. PXE drivers may be stored in either option ROMs or directly in the system BIOS. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 169 It is fundamental to understand that the register and memory blocks are not necessarily tied together. The PCI mode and processor context all affect how software views both blocks (see Figure 32 on page 170). Broadcom ® January 29, 2016 • 5718-PG108-R Page 169...
Page 170: Figure 32: Local Contexts
The following components are involved in Ethernet controller configuration space mapping: • Base Address registers • Standard mode map mode • Flat memory map mode • Indirect access mode • Configuration space header • Host memory • MAC registers Broadcom ® January 29, 2016 • 5718-PG108-R Page 170...
Page 171: Functional Overview
The Ethernet controller single function chips follow the stated technique #1— BIOS code scanning multifunctions get a target response from function(s) 1–7, but these functions are essentially shadows of function 0. Software that programs to function(s) 1–7 is remapped to function 0. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 172: Indirect Mode
PCI access modes and is a mode in itself. Note: Host software must assert the Indirect_Mode_Access bit in the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (offset: 0x68)” on page 282) to enable indirect mode. Broadcom ® January 29, 2016 • 5718-PG108-R Page 172...
Page 173: Indirect Register Access
Register_Base_Address and Register_Data registers through memory mapped by the PCI BAR register), as opposed to PCI configuration write cycles, the host software must insert a read command to the Register_Base_Address register between two consecutive writes to the Register_Base_Address and Register_Data registers. Broadcom ® January 29, 2016 • 5718-PG108-R Page 173...
Page 174: Figure 34: Register Indirect Access
BCM57XX Ethernet Controller Registers Address may be located anywhere 0x00008000 BusX DeviceY Function Z Not Accessible via Register Indirect Mode Register Base Address Register Data Register 0x00038000 Rx CPU 0x00038800 Broadcom ® January 29, 2016 • 5718-PG108-R Page 174...
Page 175: Indirect Memory Access
PCI BAR register), as opposed to PCI configuration write cycles, the host software must insert a read command to the Memory_Window_Base_Address register between two consecutive writes to the Memory_Window_Base_Address and Memory_Window_Data registers. Broadcom ® January 29, 2016 • 5718-PG108-R Page 175...
Page 176: Figure 35: Indirect Memory Access
BCM57XX Ethernet Controller PCI Configuration Space Memory Block 0x00000000 Address may be located anywhere Internal Memory BusX DeviceY Function Z Memory Base Address Address may be located anywhere 0x00020000 Memory Data Register Broadcom ® January 29, 2016 • 5718-PG108-R Page 176...
Page 177: Undi Mailbox Access
Fifteen additional receive return rings would extend the size of the Device Specific portion of the PCI Configuration Space registers. The UNDI shadow registers alias three registers in the Ethernet controller register block (see Figure 36 on page 178). Broadcom ® January 29, 2016 • 5718-PG108-R Page 177...
Page 178: Figure 36: Low-Priority Mailbox Access For Indirect Mode
BCM57XX 0x0005880 Registers Rx BD Return Ring 1 Consumer Index 0x000588F UNDI Tx BD NIC Producer Index Mailbox 0x0005980 Tx BD Ring 1 NIC Producer Index 0x00005987 0x00005BFF Not Aliased 0x00008000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 178...
Page 179: Standard Mode
BAR + 0x00000000 BAR0 PCI Configuration BAR1 Space Registers (Shadow Copy) BAR + 0x000000FF Reserved BAR + 0x000001FF High Priority Mailboxes BAR + 0x000003FF Registers BAR + 0x00007FFF Memory Window BAR + 0x0000FFFF Broadcom ® January 29, 2016 • 5718-PG108-R Page 179...
Page 180: Figure 38: Memory Window Base Address Register
Ethernet controller. Such an access may be decoded by another device, or simply go unclaimed on the PCI bus. Figure 39 on page 181 shows the relationship between the Memory_Window_Base_Address register and the Memory Window. Broadcom ® January 29, 2016 • 5718-PG108-R Page 180...
Page 181: Figure 39: Standard Mode Memory Window
Window may be located anywhere Mem Wnd Base Addr Internal Host software may access the BCM57XX Ethernet Controller local Window may be Registers memory using this located anywhere window Memory Window 0x00020000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 181...
Page 182: Figure 40: Techniques For Accessing Ethernet Controller Local Memory
Rx BD Producer Index Reserved Rx BD Return Ring 1-4 Consumer Index 32 MB Reserved 0x00180000 Tx BD Ring Host Producer Index Reserved 0x001C0000 Tx BD Ring NIC Producer Index Reserved 0x01000000 Memory 0x01FFFFFF Broadcom ® January 29, 2016 • 5718-PG108-R Page 182...
Page 183 Rx BD Return Ring 1-16 Consumer Index Reserved 0x00180000 Tx BD Ring 1-16 Host Producer Index Reserved 0x001C0000 Tx BD Ring 1-16 NIC Producer Index Reserved 0x01000000 Device External Memory Memory 0x01FFFFFF 0x00020000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 183...
Page 184: Memory Mapped I/O Registers
The Ethernet controller memory mapped I/O range may be placed anywhere in 64-bit address space (Type = 10). • The Ethernet controller deasserts the Prefetchable bit to indicate that the memory range should not be cached. Broadcom ® January 29, 2016 • 5718-PG108-R Page 184...
Page 185: Figure 42: Pci Base Address Register
Figure 43: PCI Base Address Register Bits Read in Standard Mode Binary Weighted Value: Ignored: 0x00010000 = 64K Bits 0-3 X's are don't cares XXXX XXXX XXXX XXX1 0000 0000 0000 [31:4] [2:1] Broadcom ® January 29, 2016 • 5718-PG108-R Page 185...
Page 186: Bus Interface
The following architectural components are involved in the configuration of the PCI/DMA interface: • DMA read engine • DMA write engine • DMA read FIFO • DMA write FIFO • PCIe interface • PCI state register • DMA read/write register Broadcom ® January 29, 2016 • 5718-PG108-R Page 186...
Page 187: Operational Characteristics
(PCI_State.PCI_Expansion_ROM_Desired bit is set to 1). On the other hand, if the PCI_Expansion_ROM_Desired bit cleared, then the Ethernet controller returns a value of 0x00000000. This indicates to the BIOS that no Expansion ROM is supported. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 188: Preboot Execution Environment
The MAC will consume a maximum of 375 mA in a D3 cold power management mode. The following functional blocks are integral to MAC power management: • PMSCR register • PCI Clock Control register • Miscellaneous Control register Broadcom ® January 29, 2016 • 5718-PG108-R Page 188...
Page 189: Operational Characteristics
Ethernet controller reference designs. The MAC GPIO pins are available for application specific usage; however, Broadcom encourages both software and hardware engineers to follow the Broadcom design guidelines and application notes. NIC and LOM designs use external board level logic to switch power regulators for D3 ACPI mode.
Page 190: Device State D0 (Active)
Note: The PCIe devices support the PCIe power management which is compatible with PCI bus power management. Wake on LAN “Wake on LAN Mode/Low-Power” on page 212. ™ Magic Packet is a registered trade mark of AMD. Broadcom ® January 29, 2016 • 5718-PG108-R Page 190...
Page 191: Gpio
BCM5718 Programmer’s Guide Power Management GPIO The use of GPIO pins for power management is design-specific, though Broadcom-delivered drivers use GPIO pins in the manner listed in Table 49. This usage is only applicable when the Ethernet controller is configured for a NIC design;...
Page 192: Device Acpi Transitions
D1 and D2 states are introduced for board level designs—the bits provide flexibility to the application. The Broadcom reference NIC/LOM designs do not use D1 and D2 states; therefore, host software should avoid setting these states. Before the Mac is moved into the D3 state, the clocks and GPIO must be configured (see above sections).
Page 193: Endian Control (Byte And Word Swapping)
Examples of little-endian platforms include Intel x86 and DEC Alpha. PCI assumes a little-endian memory model. PCI configuration registers are organized so that the least significant portion of the data is assigned to the lower address. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 194: Architecture
Ethernet controller maps PCI data to internal structures shown in Table 54 Table 55 on page 195. Table 54: Default Translation (No Swapping) on 64-Bit PCI Internal Byte # Internal Bit # Broadcom ® January 29, 2016 • 5718-PG108-R Page 194...
Page 195: Table 55: Default Translation (No Swapping) On 32-Bit Pci
(Little Endian) referenced on-chip data structures as they are defined in the Ethernet controller data sheet, the driver should set the Enable Endian Word Swap bit. By setting this bit, the translation would be as follows: Table 57: Internal Byte OrderingPCI Byte Ordering 0x00 0x00 Broadcom ® January 29, 2016 • 5718-PG108-R Page 195...
Page 196: Table 58: Byte Swap Enable Translation On 32-Bit Pci (No Word Swap)
Table 58: Byte Swap Enable Translation on 32-Bit PCI (No Word Swap) Internal Byte Ordering PCI Byte Ordering 0x00 0x00 0x04 0x04 Internal Byte Ordering PCI Byte Ordering 0x00 0x00 0x04 0x04 Broadcom ® January 29, 2016 • 5718-PG108-R Page 196...
Page 197: Word Swap Data And Byte Swap Data Bits
PCI AD[63:0] pins depending on the settings of those swap bits: Word Swap Data = 0, and Byte Swap Data = 0 Table 60: 64-Bit PCI Bus (WSD = 0, BSD = 0) 63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 197...
Page 198: Word Swap Data = 0, And Byte Swap Data = 1
Table 64: 64-Bit PCI Bus (WSD = 1, BSD = 0) 63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0 Table 65: 32-Bit PCI Bus (WSD = 1, BSD = 0) 31–24 23–16 15–8 7–0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 198...
Page 199: Word Swap Data = 1, And Byte Swap Data = 1
So, for a little-endian (e.g., x86) host, software should set both the Word Swap Data, and Byte Swap Data bits. This is because a little endian host will expect the first byte on the wire (byte D1) to be placed into memory at the least significant (starting) address of the packet data. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 200: Word Swap Non-Frame Data And Byte Swap Non-Frame Data Bits
Word Swap Non-Frame Data and Byte Swap Non-Frame Data bits. The following tables show how data will appear depending on the settings of those swap bits: Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 201: Word Swap Non-Frame Data = 0 And Byte Swap Non-Frame Data = 0
This requires the software to use the following big-endian data structure on the host: Table 72: Send Buffer Descriptor (Big-Endian 32-bit format) with Byte Swapping Byte # Bit # Host Address 0x00 0x04 Reserved VLAN 0x08 Length Flags 0x0C Broadcom ® January 29, 2016 • 5718-PG108-R Page 201...
Page 202: Word Swap Non-Frame Data = 1 And Byte Swap Non-Frame Data = 1
This requires the software to use the following big-endian data structure on the host: Table 73: Send Buffer Descriptor (Big-Endian 32-bit format) with Word and Byte Swapping Byte # Bit # Host Address 0x00 0x04 Length Flags 0x08 Reserved VLAN 0x0C Broadcom ® January 29, 2016 • 5718-PG108-R Page 202...
Page 203: Section 10: Ethernet Link Configuration
The link state of the Ethernet controller can also be forced by disabling both the auto-polling function and the LNKRDY signal and forcing the link status by directly writing to the MII_Status.Link_Status bit. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 204: Link Status Change Indications
// Now return the value that we read (lower 16 bits of reg) Return (Value32 & 0xffff) Writing a PHY Register // Setup the value that we are going to write to MI Communication register Broadcom ® January 29, 2016 • 5718-PG108-R Page 204...
Page 205: Phy Loopback Configuration
- Write 0x1000 to PHY register 1Eh // Force link (required for 100Base-TX) - Set MAC register 0x400[3:2] = 01b // Set MII - Set MAC register 0x400[1] // Force full-duplex operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 205...
Page 206: Phy Configuration Auto-Negotiation (10/100/1000 Speed With Half And Full Duplex Support)
// Wait up to 15ms for link to drop for (int i = 0; i < 15000; i++) { if ((phy_read(0x01) & (1 << 4) == 0) break; // Wait 10us delay_us(10); Broadcom ® January 29, 2016 • 5718-PG108-R Page 206...
Page 207 = (1 << 9); // Advertise full-duplex operation phy_write(0x09, gig); // Enable and restart autonoegotiation phy_write(0x00, ((1 << 12) | (1 << 9))); -------------------- 10Base-T Half-Duplex -------------------- uint16_t bmcr = 0; Broadcom ® January 29, 2016 • 5718-PG108-R Page 207...
Page 208 0); // Disable 10/100 autoneg advertisement phy_write(0x04, (00001b << 0)); // Write forced link speed phy_write(0x00, bmcr); ---------------------- 100Base-TX Half-Duplex ---------------------- uint16_t bmcr = 0; // Reset PHY // Enable auto-MDIX Broadcom ® January 29, 2016 • 5718-PG108-R Page 208...
Page 209 - Half duplex operation not supported at 1000Mb per 802.3 specification ---------------------- 1000Base-T Full-Duplex ---------------------- - Forced speed not supported, must use autoneg but only advertise 1000Mb speed uint16_t bmcr = 0, gig = 0; Broadcom ® January 29, 2016 • 5718-PG108-R Page 209...
Page 210: Mdi Register Access
The interface between the MAC and physical devices is with the two signals of: • MDIO clock (MDC) • Bidirectional serial data (MDIO) The details of the MDIO interface can be found in the IEEE 802.3 specification. Broadcom ® January 29, 2016 • 5718-PG108-R Page 210...
Page 211: Access Method
3. MII_Communication_Register.Command is set to 0x1. 4. MII_Communication_Register.Transaction_Data is set to 0x1000 5. MII_Communication_Register.Start_Busy is set to 1. 6. Poll Until MII_Communication_Register.Start_Busy is cleared to 0. “Configuring the GMII/MII PHY” on page 204 for example code. Broadcom ® January 29, 2016 • 5718-PG108-R Page 211...
Page 212: Wake On Lan Mode/Low-Power
MAC into the D0 (high power) state. WOL mode is a combination of PHY and MAC configurations. Both the PHY and MAC must be configured correctly to enable Broadcom’s WOL technology. The Ethernet controller provides WOL pattern filters for 10/ 100 wire speeds.
Page 213: Functional Overview
It is idle during the fourth cycle. In Gigabit mode, the pattern checker gets three pattern words from the FIFO at one time. Figure 46: WOL Functional Block Diagram Pattern Memory Tx FIFO Arbiter Data Internal Memory Pattern Power Checker Managment Rx MAC RMII GMII Broadcom ® January 29, 2016 • 5718-PG108-R Page 213...
Page 214: Operational Characteristics
(i.e., 3,5,7,9 offsets). Host software must begin all pattern matching on even byte boundaries (i.e., 2,4,6,8 offsets). The 2 bytes per unit forces even byte alignment. For example: – 0x14 (byte offset)/2 = 0x0A (register ready) – 0x28 (byte offset)/2 = 0x14 (register ready) Broadcom ® January 29, 2016 • 5718-PG108-R Page 214...
Page 215: Wol Streams
10/100 modes. The WOL pattern checker breaks frames into 2-byte pairs, so all nine comparators can begin matching data. In Figure 47 on page 216, three Ethernet frames are compared against the nine available patterns. Broadcom ® January 29, 2016 • 5718-PG108-R Page 215...
Page 216: Figure 47: Comparing Ethernet Frames Against Available Patterns (10/100 Ethernet Wol)
C2, C3 ACPI Mbuf Pointer Register Base Addr/8 A4,A5 B4, B5 00,00 ACPI Length Offset Register Length Offset ACPI length field is the max pattern size Nine pattern streams for simultaneousWOL compare Broadcom ® January 29, 2016 • 5718-PG108-R Page 216...
Page 217: Pattern Data Structure
Reserved S0 High Byte Enable Enable S0 higher byte for comparison S0 Low Byte Enable Enable S0 lower byte for comparison S1 High Byte Enable Enable S1 higher byte for comparison Broadcom ® January 29, 2016 • 5718-PG108-R Page 217...
Page 218: Firmware Mailbox
PHY. After resetting the Ethernet controller, host software should poll for the one’s complement of the T3_MAGIC_NUM before it proceeds, otherwise, boot code initialization may interfere with the host software initialization. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 219: Phy Auto-Negotiation
MAC to assert PME on the PCI bus. The RX MAC should maintain the multicast and broadcast ® settings that were previously configured by the NOS. The Microsoft power management specification states: Broadcom ® January 29, 2016 • 5718-PG108-R Page 219...
Page 220: Integrated Macs
(offset: 0x400)” on port is currently using: MII, GMII, or page 310. none. Magic_Packet_ Enable WOL pattern filtering. Detection Promiscuous_mode All frames are forwarded, without any filtering, when this bit is enabled. Broadcom ® January 29, 2016 • 5718-PG108-R Page 220...
Page 221: Wol Data Flow Diagram
5. Disable the FHDE, RDE, TDE bits of the “EMAC Mode Register (offset: 0x400)” on page 310”, and on-chip RISCs. 6. Host software must write the signature 0x4B657654 to internal memory address 0x0B50. Check for one’s complement of 0x4B657654. Broadcom ® January 29, 2016 • 5718-PG108-R Page 221...
Page 222 Management Control/Status Register (offset: 0x4C)” on page 279). The Ethernet controller asserts PME to wake up the system. Set the Power_State bits to D3 in the PCI Power Management Control/Status Register (offset: 0x4C). Broadcom ® January 29, 2016 • 5718-PG108-R Page 222...
Page 223: Flow Control
MAC will not generate flow control frames. The MAC_RX_MBUF_Low_Water_Mark register value triggers PAUSE frames to be transmitted when a threshold value is passed. Software may alter the watermark to tune system performance. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 224: Receive Mac
The receive MAC will filter pause control frames when the Keep_Pause bit is disabled. Table 85: Keep_Pause Recommended Value Register.Bit Recommended Value Receive_MAC_Mode_Control.Keep_Pause DISABLED Broadcom ® January 29, 2016 • 5718-PG108-R Page 224...
Page 225: Statistics Block
Transmit_MAC_Mode_Control.Flow_Enabled bit is set. • (MAC_RX_MBUF_Low_Water_Mark < Threshold Value) MAC resources are running low and a pause is desired. • (pause_time > 0) IEEE 802.3 MAC flow control frame is sent. Broadcom ® January 29, 2016 • 5718-PG108-R Page 225...
Page 226: Phy Auto-Negotiation
“Low Watermark Low_Water_Mark must be available before the RX Maximum Receive Frame engine can accept a frame from the Register (offset: 0x504)” on wire. page 327. Threshold value for initiating flow control. Broadcom ® January 29, 2016 • 5718-PG108-R Page 226...
Page 227: Flow Control Initialization Pseudocode
//The local physical layer was not configured to advertise Asymmetric pause Else (Auto_Neg_Link_Partner_Ability_Reg.Pause_Capable == ENABLED) Then Driver_Flow_Capability = FLOW_CONTROL_TRANSMIT_PAUSE \ | FLOW_CONTROL_RECEIVE_PAUSE Else Driver_Flow_Capability = NONE // The local physical layer was not configured to advertise Pause capability Broadcom ® January 29, 2016 • 5718-PG108-R Page 227...
Page 228 //Configure MAC Flow Control Registers if ( Driver_Flow_Capability & FLOW_CONTROL_RECEIVE_PAUSE ) Receive_MAC_Mode_Control_Register.Enable_Flow_Control = ENABLED if ( Driver_Flow_Capability & FLOW_CONTROL_TRANSMIT_PAUSE ) Then Transmit_MAC_Mode_Control_Register.Enable_Flow_Control = ENABLED // Link is up on the local PHY Broadcom ® January 29, 2016 • 5718-PG108-R Page 228...
Page 229: Section 11: Interrupt Processing
ISR may either spin and wait for the status block DMA to complete and explicitly flush the status block, or just wait for the next line interrupt. Table 88: NetXtreme Legacy Status Block Format Offset 3116 0x00 Status Word 0x04 [31:8] Reserved 0x0 [7:0]Status Tag Broadcom ® January 29, 2016 • 5718-PG108-R Page 229...
Page 230: Isr Flow
Check for differences between previous consumer index (tracked by host driver) and current consumer index in the status block. These are the Tx BDs which can be made available again to the next send operation. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 231: Legacy Status Tagging Mode
[23:0] is written with a zero value, the tag field of the mailbox register is compared with the tag field of the last status block to be DMAed to the host. If the tag returned is not equivalent to the tag of the first status block DMAed, then the controller triggers another interrupt immediately. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 232: Basic Driver Interrupt Processing Flow
2 in the M isc Local Control any posted writes in the PCI chipset. Regsiter (offset 0x6808) R ead the, Is the "U pdated bit" set in the Status Block? Broadcom ® January 29, 2016 • 5718-PG108-R Page 232...
Page 233: Interrupt Procedure
Tag to the upper 8 bits of Interrupt Mailbox 0, and 0 to the remaining bits (23 down to 0) to indicate that the ISR is done processing RX/TX. Otherwise, write 0 to Interrupt Mailbox 0 register. This step also clears existing interrupts. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 234: Host Coalescing
ISR may occasionally see stale data. The ISR may either spin and wait for the status block DMA to complete and explicitly flush the status block or just wait for the next line interrupt. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 235: Registers
Interrupt on MAC Attention (Bit 26) causes a host interrupt when an enabled MAC attention occurs • Interrupt on RX RISC Attention (Bit 25) causes a host interrupt when an enabled RX-RISC attention occurs Broadcom ® January 29, 2016 • 5718-PG108-R Page 235...
Page 236: Msi
Host Memory Memory To clarify second issue in traditional interrupt scheme, an example is given. The Ethernet controller receives one or more packets from the networks. The Ethernet controller does the following: Broadcom ® January 29, 2016 • 5718-PG108-R Page 236...
Page 237: Message Signaled Interrupt
Host Memory Similar example in traditional interrupt scheme is used again here to illustrate MSI concept. The Ethernet controller receives one or more packets from the networks. The Ethernet controller does the following: Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 238: Pci Configuration Registers
This is a 16-bit field. The least significant three bits can be modified by the Ethernet controller when it writes MSI message to host. The DWORD data for the MSI message is depicted as shown in Figure Figure 52: MSI Data FIeld All 0’s 16-bit MSI_Data Broadcom ® January 29, 2016 • 5718-PG108-R Page 238...
Page 239: Host Coalescing Engine
(bits 3:1) of Message Control register (offset 0x5A). The least significant 3-bits of the MSI message generated by the device are always taken from bits 6:4 of Host_Coalesing_Mode register (offset 0x3C00). Broadcom ® January 29, 2016 • 5718-PG108-R Page 239...
Page 240: Msi-X
Thus, the BCM5718 family offers two vector modes within the MSI-X mode: • Single Vector mode • Multivector mode Each of these two modes in turn offers the following submodes: • Single Vector mode (Restrict to Vector#0) – Single Vector RSS mode Broadcom ® January 29, 2016 • 5718-PG108-R Page 240...
Page 241: Table 90: Msi-X Vector Mode Selection
– Rx Return Ring Indication (Active only when RSS is Disabled) – Send Completion – Link Status Change – Error/Attention – Rx Return Ring3 through Ring0 Indications • IOV mode: Vector#0—Aggregate of the following: Broadcom ® January 29, 2016 • 5718-PG108-R Page 241...
Page 242 - Transmit queue 2 Completion (in Multi TXQ mode) - Link Status Change – Vector#16–Aggregate of the following - VRQ16 Indication - Transmit queue 16 Completion (in Multi TXQ mode) - Link Status Change Broadcom ® January 29, 2016 • 5718-PG108-R Page 242...
Page 243 There could be instances when the OS enables RSS but allocates only one MSI-X vector to our device. The Broadcom driver would resort to choosing Single Vector mode in such a scenario. Note: When MSI-X is disabled, INTx or MSI continue to function as in legacy device implementations.
Page 244: Msi-X Plumbing
Address Indication Items Address Indication Items Comments Legacy 0x3C3C, 0x200 (*) ALL 0x200(*) ALL Legacy Status Block. 0x3C38 Used by INTx or MSI. Also used in MSI-X Single-Vector RSS mode or IOV mode Broadcom ® January 29, 2016 • 5718-PG108-R Page 244...
Page 245 IOV mode Index 0x3D18, 0x220 VRQ4 RR Prod 0x220 (*) Rx Return Ring 3 Prod Vector#3 -- Vector#4. Index Index SBD4 Cons Index 0x3D1C SBD4 Cons Index ‘RBD 4 Cons Index Broadcom ® January 29, 2016 • 5718-PG108-R Page 245...
Page 246: Single-Vector Rss Mode Status Block Format
Note: Although High Priority INT Mail Boxes are DWORD (32-bit) registers, the original four were placed on QWORD (64-bit) boundaries for legacy PCI 64-bit target access purposes. Broadcom’s PCIe does not allow 64-bit target accesses. Thus, the new Mailboxes are being placed 32-bits apart;...
Page 247: Single-Vector Iov Mode Status Block Format
Jumbo RBD Ring 1 Consumer Index 0x54 Standard RBD Ring 2 Consumer Index Jumbo RBD Ring 2 Consumer Index 0x58 Standard RBD Ring 3 Consumer Index Jumbo RBD Ring 3 Consumer Index …….. ………………………… ………………………. Broadcom ® January 29, 2016 • 5718-PG108-R Page 247...
Page 248: Multivector Rss Mode Status Block Format
Bit [0]: Update-Bit • Bit [1]: Link Status Change • Bit [2]: Error/Attention • Bit [3]: Resvd–always 0 • Bit [4]: Resvd–always 0 • Bit [5]: Resvd–always 0 • Bits [31:6]: Reserved 0x0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 248...
Page 249: Multivector Iov Mode Status Block Format
Bit [2]: Error/Attention • Bits[5:3]: Resvd–always 0x0 • Bit [6]: Change in VRQ Active Bit Map • Bits [14:7]: Resvd–always 0x0 • Bit[15]: VRQ Active Bit-Map[16] • Bits [31:16]: VRQ Active Bit-Map[15:0] Broadcom ® January 29, 2016 • 5718-PG108-R Page 249...
Page 250: Msi-X Capability Structure
BCM5718 family, both BIRs have a hard-wired value of 0x4, which implies BAR4 and BAR5. Note: BAR4 and BAR5 must support 8/16- and 32-bit accesses from the host. However, unaligned 16/32-bit access support are not required. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 251: Msi-X Data Structures
Mask bits found in each Table Entry determine whether a vector is masked or not. – Table Size: This field may declare a value of either 5 or 17. This is accomplished by Boot Code programming the appropriate Private Register of the PCIe core. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 252: Table 99: Msi-X Table And Pba Structures In Bcm5718 Family
Msg#2 Data Msg#2 Addr H Msg#2 Addr L 0x20 Vec#1 Control Msg#1 Data Msg#1 Addr H Msg#1 Addr L 0x10 Vec#0 Control Msg#0 Data Msg#0 Addr H Msg#0 Addr L 0x00 Broadcom ® January 29, 2016 • 5718-PG108-R Page 252...
Page 253: Msi-X Cognizant Host Coalescing
For host environments where receive interrupt latency must be very low, and the host is not close to saturation, it is recommended that this register be set to 1. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 254: Send Coalescing Ticks Register (Offset: 0X3C0C)
This register must be initialized by host software. A value of 0 in this register disables the send max BD coalescing logic. In this case, status block Broadcom ®...
Page 255: Receive Max Coalesced Bd Count During Interrupt Register (Offset 0X3C18)
Receive [n] Max Coalesced BD Count During Interrupt Register • Send [n] Max Coalesced BD Count During Interrupt Register Where, n ranges from 1 through 16. The legacy HC Parameter registers are now called HC Parameter Set [0]. Broadcom ® January 29, 2016 • 5718-PG108-R Page 255...
Page 256: Table 100: Msi-X Host Coalescing Parameters
VRQ 3 0x3DB4 RSS 2 ----- RSS 2 RMCBCR[3] 0x3DB8 TXQ 3 0x3DB8 0x3DB8 TXQ 3 0x3DB8 SMCBCR[3] 0x3DBC ----- 0x3DBC ----- RMCBCDIR[3] 0x3DC0 0x3DC0 0x3DC0 0x3DC0 SMCBCDIR[3] 0x3DC4 ----- 0x3DC4 ----- Broadcom ® January 29, 2016 • 5718-PG108-R Page 256...
Page 257 SEND MAX COALESCED BD COUNT REGISTER[n] RMCBCDIR[n] RECEIVE MAX COALESCED BD COUNT DURING INTERRUPT REGISTER[n] SMCBCDIR[n] SEND MAX COALESCED BD COUNT DURING INTERRUPT REGISTER[n] 0x55AA New Registers in BCM5718 family (legend) Broadcom ® January 29, 2016 • 5718-PG108-R Page 257...
Page 258: Msi-X One Shot Mode
HC parameters or MSI-X feature in general, and some do not apply equally. Such controls are listed here for clarity: Broadcom Tagged Status Mode (0x68[9]) Enabled by setting the Status Tagged Status Mode bit of the Miscellaneous Host Control register. When enabled, a unique eight-bit tag value is inserted into the Status Block Status Tag at location 7:0.
Page 259: Clear Interrupt, Mask Interrupt, Mask Mode (0X68[0], 0X68[1], 0X68[8])
Do Not Interrupt On Receives (0x6800[14]) If set, an interrupt is not generated upon a Receive Return Ring producer update. This bit applies equally to vector#0 through vector#16 in Multivector mode. Broadcom ® January 29, 2016 • 5718-PG108-R Page 259...
Page 260: End Of Receive Stream Interrupt
MSI-X Vector# 16 through 1. These bits are self-clearing. As defined in Legacy 12:0 End Stream Debounce Register (Offset 0x3cd4) Default DESCRIPTION Name Bits Access Value As defined in Legacy Reserved 30:16 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 260...
Page 261 FSM triggers an interrupt/MSI-X. The counter basically de-bounces effects of IPG or short gaps among packets within a burst. The counter counts in Core-Clocks. Broadcom ® January 29, 2016 • 5718-PG108-R Page 261...
Page 262: Other Configuration Controls
INTA signal. Note that the During Interrupt Coalescence registers are only used when the Mailbox 0 is set. Broadcom Tagged Status Mode Enabled by setting the Status Tagged Status mode bit of the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (offset: 0x68)”...
Page 263: Section 12: Io Virtualization (Iov)
During boot-up, if the IOV-Mode is not chosen, the chip will operate in the Legacy Mode which is akin to the operation of previous NetXtreme devices. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 264: Data Structure And Register Changes For Iov
EMAC collects basic statistics on an individual generic VRQ basis. Though the accumulation mechanism remains the same, i.e., these registers are Clear-On-Read, these statistic registers are independent of the aggregated EMAC statistics registers for LAN and APE (see “VRQ Statistics” on page 454). Broadcom ® January 29, 2016 • 5718-PG108-R Page 264...
Page 265: Msi-X Vectors Changes
“Send BD Initiator Mode Register (offset: 0x1800)” on page 353). • SEND_BD_FETCH_THRESHOLD_REG (Offset: 0x1850) This is a newly added register (see “Send BD Fetch Threshold Register (offset: 0x1850)” on page 355). Broadcom ® January 29, 2016 • 5718-PG108-R Page 265...
Page 266: Iov - Receive Side
OS images. Therefore, it implies that each VRQ shall also be associated with an independent receive indication queue, which is nothing but an independent Receive Return Ring (refer to Figure 53 on page 267 for additional information. Broadcom ® January 29, 2016 • 5718-PG108-R Page 266...
Page 267: Iov - Transmit Side
• Multiple Send Rings could be enumerated only in conjunction to either IOV-Mode or RSS Mode • All 16 Send Rings may be enabled in conjunction of IOV Mode • Up to 4 Send Rings may be enabled in conjunction of RSS Mode Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 268 SBD cache – physically it is a single SRAM, but is divided into 16 equal address regions. Each such address range shall serve as a private SBD cache to a Send Ring. The total size of the SBD cache is thus 16 KB. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 269: Section 13: Ethernet Controller Register Definitions
Receive BD Initiator 0x2C1C–0x2FFF Unused RBDC 0x3000–0x33FF 0x3000–0x300F Receive BD Completion 0x3010–0x33FF Unused CMPU 0x3400–0x37FF 0x3400–0x35FF Central Power Management Unit 0x3600–0x3687 Unused 0x3800–0x3BFF 0x3800–0x3817 Debug Unit (UART) 0x3900–0x3907 Chip Debug 0x3908–0x3BFF Unused Broadcom ® January 29, 2016 • 5718-PG108-R Page 269...
Page 270 0x703C–0x73FF Unused UART 0x7800–0x7BFF 0x7800–0x781F Debug UART Modem 0x7820–0x7BFF Unused TL-DL-PL Port 0x7C00–0x7FFF 0x7C00–0x7FFF PCIe Core Private Register Access to TL, DL & PL ****** 0x10000–0x18FFF APE Access 0x19000–0x193FF Management Filters Broadcom ® January 29, 2016 • 5718-PG108-R Page 270...
Page 271: Pci Configuration Registers
Does not apply to PCIE Capabilities List This bit is tied high to indicate that the device supports a capability list. The list starts at address 0x40. Interrupt Status Indicates this device generated an interrupt Broadcom ® January 29, 2016 • 5718-PG108-R Page 271...
Page 272 This bit indicates that the device does not support I/O space access because it is zero and can not be modified. IO transactions targeting this device return completion with UR status. Broadcom ® January 29, 2016 • 5718-PG108-R Page 272...
Page 273: Pci Classcode And Revision Id Register (Offset: 0X08)
This register does not apply to PCI express and must be hardwired to zero Cache Line Size This field is implemented by PCIE device as a read/ write field for legacy compatibility purposes. Broadcom ® January 29, 2016 • 5718-PG108-R Page 273...
Page 274: Base Address Register 1 (Offset: 0X10)
64-bit address space. Path = i_cfg_func.i_cfg_private. Space This bit indicates that BAR_2 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private. Broadcom ® January 29, 2016 • 5718-PG108-R Page 274...
Page 275: Base Address Register 4 (Offset: 0X1C)
64 bit address decode. These bits must be set to zero for the card to respond to single address cycle requests. This value is sticky and only reset by HARD Reset. Path = i_cfg_func.i_cfg_public.i_cfg_dec. Broadcom ® January 29, 2016 • 5718-PG108-R Page 275...
Page 276: Cardbus Cis Pointer Register (Offset: 0X28)
BCM5718 Programmer’s Guide PCI Configuration Registers Cardbus CIS Pointer Register (offset: 0x28) This register is reset by Hard Reset. Default Name Bits Access Value Description Cardbus CIS 31:0 N/A for PCIE Device Pointer Broadcom ® January 29, 2016 • 5718-PG108-R Page 276...
Page 277: Subsystem Id/Vendor Id Register (Offset: 0X2C)
PCI address space of a linked list of new capabilities. The capabilities are PCI-X, PCI Power Management, Vital Product Data (VPD), and Message Signaled Interrupts (MSI) is supported. Broadcom ® January 29, 2016 • 5718-PG108-R Page 277...
Page 278: Interrupt Register (Offset: 0X3C)
3: Use Interrupt C 4: Use Interrupt D Interrupt Line 0x00 Identifies interrupt routing information INT Mailbox Register (offset: 0x40–0x44) Default Name Bits Access Value Description Indirect Interrupt mail box 63:0 Interrupt Mailbox Broadcom ® January 29, 2016 • 5718-PG108-R Page 278...
Page 279: Power Management Capability Register (Offset: 0X48)
A value of 011b indicates that this function complies with revision 1.2 of the PCI PM specification. PM Next 15:8 0x58 Points to the next capabilities block which is Broadcom Vendor Capabilities Specific Capability Header PM Capability 0x01 Identifies this item as Power management capabilities Power Management Control/Status Register (offset: 0x4C) This register is reset by Hard Reset.
Page 280 PM_STATE bits are read from register space. The idea of these registers is to a) Provide compatible operation to 5701 b) Allow implementation of other power states though firmware. Broadcom ® January 29, 2016 • 5718-PG108-R Page 280...
Page 281: Msi Capability Header (Offset: 0X58)
CAP_ENA register in the PCI register space. MSI capability ID The 8-bit MSI Capability ID is set to 5 to indicate that the next 8 bytes are a Message Signaled Interrupt capability block. Broadcom ® January 29, 2016 • 5718-PG108-R Page 281...
Page 282: Msi Lower Address Register (Offset: 0X5C)
Set this bit to enable log header due to overflow Boundary check Set this bit to enable crossing 4 KB boundary check Byte enable Rule Check Set this bit to enable the byte enable rule check Broadcom ® January 29, 2016 • 5718-PG108-R Page 282...
Page 283: Dma Read/Write Control Register (Offset: 0X6C)
DMA Read/Write Control Register (Offset: 0x6C) Default Name Bits Access Value Description Reserved 31:29 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 283...
Page 284 3: 512B 4:512+256B 5:1024+512B 6:2048B 7:4096B Reserved – Disable_64B_cache_alignment 1 Disable 64B cache alignment for DMA write to Host memory Disable_32B_cache_alignment 0 Disable 32B cache alignment for DMA write to Host memory Broadcom ® January 29, 2016 • 5718-PG108-R Page 284...
Page 285: Pci State Register (Offset: 0X70)
Force PCI Retry for accesses to Expansion ROM region if enabled PCI Expansion ROM Desired 5 Enable PCI ROM base address register to be visible to the PCI host Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 285...
Page 286: Reset Counters Initial Values Register (Offset: 0X74)
Window data register Reserved – Register Data Register (offset: 0x80) Default Name Bits Access Value Description Register Data Register 31:0 Register Data at the location pointed by the Register Base Register Broadcom ® January 29, 2016 • 5718-PG108-R Page 286...
Page 287: Memory Data Register (Offset: 0X84)
UNDI Receive BD Standard Producer Ring Producer Index Mailbox Register (offset: 0x98–0x9C) Default Name Bits Access Value Description UNDI Receive BD Standard 63:0 UNDI Receive BD Std. Ring Producer Index Ring Producer Index Mailbox Broadcom ® January 29, 2016 • 5718-PG108-R Page 287...
Page 288: Msi-X Capabilities Registers
MSIX_PBA_BIR_OFF – 0xa8 Default Name Bits Access Value Description TABLE_OFFSET 31:3 Path = i_cfg_func.i_cfg_private TABLE_BIR Indicates which one of functions BAR is used to map MSI-X table into memory space. Path = i_cfg_func.i_cfg_private Broadcom ® January 29, 2016 • 5718-PG108-R Page 288...
Page 289: Pcie Capabilities Registers
2h. Path= cfg_defs PCIE_NEXT_CAP_PTR 15:8 This registers contains the pointer to the next PCI capability structure. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux PCIE_CAP_ID 0x10 This register contains the PCIExpress Capability ID. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux Broadcom ® January 29, 2016 • 5718-PG108-R Page 289...
Page 290: Device_Capability - 0Xb0
Path= i_cfg_func.i_cfg_private unused0 MAX_PL_SIZE_SUPPORTE Max Payload Size Supported. These bits are programmable from the register space and default value is based on define in version.v file. Path= i_cfg_func.i_cfg_private Broadcom ® January 29, 2016 • 5718-PG108-R Page 290...
Page 291: Device_Status_Control - 0Xb4
Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap. RELAX_ORDERING_ENABL Relax Ordering Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap. U_REQ_REPORT_EN 0:pr Unsupported Request Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap. Broadcom ® January 29, 2016 • 5718-PG108-R Page 291...
Page 292: Link_Capability - 0Xb8
0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap CLK_PWR_MGMT Clock Power Management. These bits are programmable through register. The feature itself has to be enabled in version.v Path= i_cfg_func.i_cfg_private Broadcom ® January 29, 2016 • 5718-PG108-R Page 292...
Page 293 RES_0 Reserved L0s entry supported RES_2 Reserved L0S_L1 L0s and L1 supported – end_of_table Path= i_cfg_func.i_cfg_private Value used by internal logic is the smaller of the value programmed for each function Broadcom ® January 29, 2016 • 5718-PG108-R Page 293...
Page 294: Link_Status_Control - 0Xbc
Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. RC: N/A and hardwired to 0. EP: Not implemented and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Broadcom ® January 29, 2016 • 5718-PG108-R Page 294...
Page 295 Requesting PHY to disable the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Read Completion Boundary. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value Name Description 64 Bytes 128 Bytes – end_of_table Unused0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 295...
Page 296: Slot_Capability - 0Xc0
Name Bits Access Value Description Unused 31:0 – ROOT_STATUS – 0xcc This register is not applicable for EP and hardwired to 0. Default Name Bits Access Value Description Unused 31:0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 296...
Page 297: Device_Capability_2 - 0Xd0
IDO Request Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Requests it initiates. Unused0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 297...
Page 298: Link_Capability_2 - 0Xd8
Description LINK_STATUS_2 31:17 Placeholder for Gen2 CURR_DEEMPH_LEVEL curr_deemph_level Path = pl_top Unused0 15:13 – CFG_COMPLIANCE_DEEM Compliance De-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap CFG_COMPLIANCE_SOS Compliance SOS. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap CFG_ENTER_MOD_ Enter Modified Compliance. COMPLIANCE Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Broadcom ® January 29, 2016 • 5718-PG108-R Page 298...
Page 299 Not Supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap ENTER_COMPLIANCE S/W instructs link to enter compliance mode. Value used by internal logic is set when either function has this bit enabled. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Broadcom ® January 29, 2016 • 5718-PG108-R Page 299...
Page 300: Slot_Capability_2 - 0Xe0
For 5717 B0, value is 0x05717100: • 5718 A0, value is 0x05717000 • 5718 B0, value is 0x05717100 • 5719 A0, value is 0x05719000 • 5719 A1, value is 0x05719100 • 5720 AO, value is 0x05720000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 300...
Page 301: Advanced Error Reporting Enhanced Capability Header (Offset: 0X100)
Data Link Protocol Error RW1CS 0 This bit is set when a Data Link Protocol error Status occurs. Reserved – Training Error Status RW1CS 0 This bit is set when a training error occurs. Broadcom ® January 29, 2016 • 5718-PG108-R Page 301...
Page 302: Uncorrectable Error Mask Register (Offset: 0X108)
Setting this bit will mask poisoned TLP error. Reserved 11:5 – Data Link Protocol Error Mask 4 Setting this bit will mask data link protocol error. Reserved – Training Error Mask Setting this bit will mask training error. Broadcom ® January 29, 2016 • 5718-PG108-R Page 302...
Page 303: Uncorrectable Error Severity Register (Offset: 0X10C)
Data Link Protocol Error This bit controls the severity Severity 0 = nonfatal 1 = fatal Reserved – Training Error Severity This bit controls the severity 0 = nonfatal 1 = fatal Broadcom ® January 29, 2016 • 5718-PG108-R Page 303...
Page 304: Correctable Error Status Register (Offset: 0X110)
Bad DLLP Mask Setting this bit masks Bad DLLP errors. Bad TLP Mask Setting this bit masks Bad TLP errors. Reserved – Receiver Error Mask Setting this bit masks Receiver errors. Broadcom ® January 29, 2016 • 5718-PG108-R Page 304...
Page 305: Advanced Error Capabilities And Control Register (Offset: 0X118)
Header Byte 6 15:8 – The TLP header of the transaction that has incurred a failure. Header Byte 7 – The TLP header of the transaction that has incurred a failure. Broadcom ® January 29, 2016 • 5718-PG108-R Page 305...
Page 306: Header Log Register (Offset: 0X124)
General mail box (High Priority Mailbox) Register (offset: 0x220–0x25c) Reload Statistics mail box (High Priority Mailbox) Register (offset: 0x260–0x264) Broadcom ® January 29, 2016 • 5718-PG108-R Page 306...
Page 307: High Priority Mailbox Registers
The Receive BD Return Ring 0 Consumer Index Register contains the index of the last buffer descriptor for Receive Return Ring 0 that has been consumed. Host software writes this register whenever it updates the return ring 1. This register must be initialized to 0. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 308: Receive Bd Return Ring 1 Consumer Index Register (Offset: 0X288-0X28F)
Ring Producer RX Return Ring RX Return Ring Index Index Consumer Index Comments Producer Index 0x270 UNDI – 0x98 UNDI – 0x88 64-bit Registers 0x3C80 HP – 0x268 HP – 0x280 Broadcom ® January 29, 2016 • 5718-PG108-R Page 308...
Page 309: Ethernet Mac (Emac) Registers
NIC Diagnostic Standard RBD Consumer Index [1 – 16] == 0x3F40–0x3F7C • NIC Diagnostic Jumbo RBD Consumer Index [1 – 16] == 0x3F80–0x3FFC Ethernet MAC (EMAC) Registers All registers reset are core reset unless specified. Broadcom ® January 29, 2016 • 5718-PG108-R Page 309...
Page 310: Emac Mode Register (Offset: 0X400)
This bit is self-clearing. Enable RX Statistics Enable receive statistics external updates. Reserved – Max Defer Enable Max Deferral checking statistic. Enable TX Bursting Enable transmit bursting in Gigabit half-duplex mode. Broadcom ® January 29, 2016 • 5718-PG108-R Page 310...
Page 311: Emac Status Register (Offset: 0X404)
AP Error Auto-polling interface needs service. Generates an attention when enabled. Clear this attention using the Auto-polling Status register MII Interrupt Management interface is signaling an interrupt Generates an attention when enabled. Broadcom ® January 29, 2016 • 5718-PG108-R Page 311...
Page 312: Emac Event Enable Register (Offset: 0X408)
Interface is signaling an interrupt. MII Completion Enable attention when the Management Interface transaction has completed. Reserved 21:13 – Link State Changed Enable attention when the link has changed state. Reserved 11:0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 312...
Page 313: Led Control Register (Offset: 0X40C)
SPD100LEDB = Link 100 and valid data or idle • SPD1000LEDB = Link10000 and valid data or idle • TRAFFICLEDB = PHY RCVLED or PHY XMTLED 11: Same as PHY mode 1 Traffic LED Status – Broadcom ® January 29, 2016 • 5718-PG108-R Page 313...
Page 314: Emac Mac Addresses 0 High Register (Offset: 0X410)
Upper 2-bytes of this node's MAC address. EMAC MAC Addresses 0 Low Register (offset: 0x414) Default Name Bits Access Value Description MAC Address Low 31:0 Lower 4-byte of this node's MAC address. Broadcom ® January 29, 2016 • 5718-PG108-R Page 314...
Page 315: Emac Mac Addresses 1 High Register (Offset: 0X418)
Upper 2-bytes of this node's MAC address. EMAC MAC Addresses 3 Low Register (offset: 0x42C) Default Name Bits Access Value Description MAC Address Low 31:0 Lower 4-byte of this node's MAC address. Broadcom ® January 29, 2016 • 5718-PG108-R Page 315...
Page 316: Wol Pattern Pointer Register (Offset: 0X430)
Note: If the MTU value in register 0x43C[15:0] is greater than the value in 0x2458[15:2], then the driver MUST configure jumbo frame support and fill the jumbo receive producer rings. Broadcom ® January 29, 2016 • 5718-PG108-R Page 316...
Page 317: Gigabit Pcs Test Register (Offset: 0X440)
25:21 0x8: SGMII SerDes Port0. 0x9: SGMII SerDes Port1. as strapped: External PHY Port0 as strapped: External PHY Port1 Register Address 20:16 Address of the register to be read or written. Broadcom ® January 29, 2016 • 5718-PG108-R Page 317...
Page 318: Mii Status Register (Offset: 0X450)
If cleared, the device will obtain the link status information from the state of the LINKRDY input signal. Reserved – Auto_control – Use Short Preamble Use short preamble while polling, if set. Broadcom ® January 29, 2016 • 5718-PG108-R Page 318...
Page 319: Autopolling Status Register (Offset: 0X458)
If the FIFO still does not have sufficient space, TCE simply drops the copy of the HTX2B-bound packet and moves on. The number of clocks to count-down is programmable at register 0x464[31:24]. Broadcom ® January 29, 2016 • 5718-PG108-R Page 319...
Page 320 When set, the Pause time value set in the transmitted PAUSE frames is 0xFFFF. The default value for PAUSE time is 0x1FFF Enable Big Backoff MAC will use larger than normal back-off algorithm. Broadcom ® January 29, 2016 • 5718-PG108-R Page 320...
Page 321: Transmit Mac Status Register (Offset: 0X460)
When multiplied by 2, this field indicates the number of bytes in the entire IPG. Slot Time Length When multiplied by 2, this field indicates the number of bytes in the slot time. Broadcom ® January 29, 2016 • 5718-PG108-R Page 321...
Page 322: Receive Mac Mode Register (Offset: 0X468)
IPV6 packets. This bit should be set to 0 if IPv6 RX is disabled. RSS TCP/IPV4 Hash Enable When this bit is set, 4-tuple hashes are enabled for TCP over IPV4 packets. Broadcom ® January 29, 2016 • 5718-PG108-R Page 322...
Page 323 Until it is completely halted, it remains 1 when read. Reset When this bit is set to 1, the Receive MAC state machine will be reset. This is a self-clearing bit. Broadcom ® January 29, 2016 • 5718-PG108-R Page 323...
Page 324: Receive Mac Status Register (Offset: 0X46C)
Hash value 31:0 Hash value for multicast destination address matching. MAC Hash Register 3 (offset: 0x47C) Default Name Bits Access Value Description Hash value 31:0 Hash value for multicast destination address matching. Broadcom ® January 29, 2016 • 5718-PG108-R Page 324...
Page 325: Receive Rules Control Registers (Offset: 0X480 + 8*N)
The number of valid classes is the number of active queues divided by the Number of Interrupt Distribution Groups. Ring 1 has the highest priority. Offset Number of bytes offset specified by the header type. Broadcom ® January 29, 2016 • 5718-PG108-R Page 325...
Page 326: Receive Rules Value/Mask Registers (Offset: 0X484 + 8*N)
Specifies the default class of service for the Class frame if no rules are matched. A value of 1 is the highest priority. A value of zero will cause the frame to be discarded. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 326...
Page 327: Low Watermark Maximum Receive Frame Register (Offset: 0X504)
Access Value Description MAC Low Address 31:0 0x0000 Lower 4-bytes of APE's [1–4]th unicast address. SGMII Control Register (offset: 0x5B0) Default Name Bits Access Value Description Reserved – – – – Broadcom ® January 29, 2016 • 5718-PG108-R Page 327...
Page 328: Sgmii Status Register (Offset: 0X5B4)
HTX2B Perfect Match[1–4] LO Reg (offset: 0x4884, 0x488C, 0x4894, 0x489C) There are four Perfect (Destination Address) Match registers in DMAR for HTX2B. These registers hold the lower two octets of the matching address. Broadcom ® January 29, 2016 • 5718-PG108-R Page 328...
Page 329: Htx2B Protocol Filter Reg (Offset: 0X6D0)
Duplicate–IPv6 Neighbor Advertisement Duplicate–NetBios Packet Duplicate–DHCP Server Packet Duplicate–DHCP Client Packet Duplicate–ARP Packet Duplicate–HTX2B Perfect Match Address[3] Duplicate–HTX2B Perfect Match Address[2] Duplicate–HTX2B Perfect Match Address[1] Duplicate–HTX2B Perfect Match Address[0] Unused 15:11 Broadcom ® January 29, 2016 • 5718-PG108-R Page 329...
Page 330 Advertisement Enable–IPv6 Neighbor Advertisement Enable–NetBios Packet Enable–DHCP Server Packet 6 Enable–DHCP Client Packet Enable–ARP Packet Enable–HTX2B Perfect Match Address[3] Enable–HTX2B Perfect Match Address[2] Enable–HTX2B Perfect Match Address[1] Enable–HTX2B Perfect Match Address[0] Broadcom ® January 29, 2016 • 5718-PG108-R Page 330...
Page 331: Htx2B Global Filter Reg (Address: 0X6D4)
23:20 The RSS_ring value for entry 10. table_entry11 19:16 The RSS_ring value for entry 11. table_entry12 15:12 The RSS_ring value for entry 12. table_entry13 11:8 The RSS_ring value for entry 13. Broadcom ® January 29, 2016 • 5718-PG108-R Page 331...
Page 332: Indirection Table Register 3 (Offset: 0X638)
The RSS_ring value for entry 27. table_entry28 15:12 The RSS_ring value for entry 28. table_entry29 11:8 The RSS_ring value for entry 29. table_entry30 The RSS_ring value for entry 30. table_entry31 The RSS_ring value for entry 31. Broadcom ® January 29, 2016 • 5718-PG108-R Page 332...
Page 333: Indirection Table Register 5 (Offset: 0X640)
The RSS_ring value for entry 51. table_entry52 15:12 The RSS_ring value for entry 52. table_entry53 11:8 The RSS_ring value for entry 53. table_entry54 The RSS_ring value for entry 54. table_entry55 The RSS_ring value for entry 55. Broadcom ® January 29, 2016 • 5718-PG108-R Page 333...
Page 334: Indirection Table Register 8 (Offset: 0X64C)
The RSS_ring value for entry 75. table_entry76 15:12 The RSS_ring value for entry 76. table_entry77 11:8 The RSS_ring value for entry 77. table_entry78 The RSS_ring value for entry 78. table_entry79 The RSS_ring value for entry 79. Broadcom ® January 29, 2016 • 5718-PG108-R Page 334...
Page 335: Indirection Table Register 11 (Offset: 0X658)
The RSS_ring value for entry 99. table_entry100 15:12 The RSS_ring value for entry 100. table_entry101 11:8 The RSS_ring value for entry 101. table_entry102 The RSS_ring value for entry 102. table_entry103 The RSS_ring value for entry 103. Broadcom ® January 29, 2016 • 5718-PG108-R Page 335...
Page 336: Indirection Table Register 13 (Offset: 0X664)
The RSS_ring value for entry 123. table_entry124 15:12 The RSS_ring value for entry 124. table_entry125 11:8 The RSS_ring value for entry 125. table_entry126 The RSS_ring value for entry 126. table_entry127 The RSS_ring value for entry 127. Broadcom ® January 29, 2016 • 5718-PG108-R Page 336...
Page 337: Hash Key Register 0 (Offset: 0X670)
Hash_key[311:304] 15:8 The 39th byte of the hash_key. The bits are in the big endian format. Hash_key[319:312] The 40th byte of the hash_key. The bits are in the big endian format. Broadcom ® January 29, 2016 • 5718-PG108-R Page 337...
Page 338: Receive Mac Programmable Ipv6 Extension Header Register (Offset: 0X6A0)
These bits contain the programmable extension Header Type #2 header value for programmable header #2. Programmable Extension These bits contain the programmable extension Header Type #1 header value for programmable header #1. Broadcom ® January 29, 2016 • 5718-PG108-R Page 338...
Page 339: Statistics Registers
A count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision. dot3StatsDeferredTransmissions (offset: 0x824) A count of frames for which the first transmission attempt on a particular interface is delayed because of the medium is busy. Broadcom ® January 29, 2016 • 5718-PG108-R Page 339...
Page 340: Dot3Statsexcessivetransmissions (Offset: 0X82C)
Set1 is owned by Host Driver and Set2 is owned by APE. HTX2B Stats Registers resides in TX-MAC and the B2HRX Stats Registers reside in RDI. A counter is automatically reset to 0 by HW upon a Read Operation by software. All counters roll over. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 341: Htx2B Statistics
The number of octets received on the interface, including frame characters. ifHCINOctets_bad (offset: 0x884) The number of bad octets received on the interface. etherStatsFragments (offset: 0x888) A frame size that is less than 64 bytes with a bad FCS. Broadcom ® January 29, 2016 • 5718-PG108-R Page 341...
Page 342: Ifhcinucastpkts (Offset: 0X88C)
MAC control frames with no pause command. xoffStateEntered (offset: 0x8AC) Transmitting is disabled. dot3StatsFramesTooLongs (offset: 0x8B0) A count of frames received on a particular interface that exceeds the maximum permitted frame size. Broadcom ® January 29, 2016 • 5718-PG108-R Page 342...
Page 343: Etherstatsjabbers (Offset: 0X8B4)
The number of inbound packets selected to be discarded (even though an error was not detected) to prevent the packets from being delivered to a higher layer protocol. Ifinerror:0x2254 The number of inbound packets containing errors that prevented the packets from being delivered to a higher- layer protocol. Broadcom ® January 29, 2016 • 5718-PG108-R Page 343...
Page 344: Ape_Network_Stats_Regs (Offsets 0X900-0X9Bc)
Receive Statistics IFHCINOCTETS_GOOD 0x0980 IFHCINOCTETS_BAD 0x0984 ETHERSTATSFRAGMENTS 0x0988 IFHCINUCASTPKTS 0x098C IFHCINMULTICASTPKTS 0x0990 IFHCINBROADCASTPKTS 0x0994 DOT3STATSFCSERRORS 0x0998 DOT3STATSALIGNMENTERRORS 0x099C XONPAUSEFRAMESRECEIVED 0x09A0 XOFFPAUSEFRAMESRECEIVED 0x09A4 MACCONTROLFRAMESRECEIVED 0x09A8 XOFFSTATEENTERED 0x09AC DOT3STATSFRAMESTOOLONG 0x09B0 ETHERSTATSJABBERS 0x09B4 ETHERSTATSUNDERSIZEPKTS 0x09B8 Broadcom ® January 29, 2016 • 5718-PG108-R Page 344...
Page 345: Send Data Initiator Registers
Stats Overflow Attention A statistics managed by Send Data Initiator has overflowed. Reserved – Send Data Initiator Statistics Control Register (offset: 0xC08) Default Name Bits Access Value Description Reserved 31:5 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 345...
Page 346: Send Data Initiator Statistics Mask Register (Offset: 0Xc0C)
1. Not affected by Statistics Enable Mask. Bits 15:0 correspond to statistics for Class of Service 16:1 Local Statistics Register (offset: 0xC80–0xCDF) Default Name Bits Access Value Description Reserved 31:10 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 346...
Page 347: Tcp Segmentation Control Registers
Specifies the length of data to be transmitted. Although firmware can specify up to 64 KB, it should not attempt to program more than 8 KB because it would exceed the size of TXMBUF. Broadcom ® January 29, 2016 • 5718-PG108-R Page 347...
Page 348: Dma Flag Register For Tcp Segmentation (Offset: 0Xcec)
Following the completion of this DMA, a host interrupt is generated. Last BD in Frame – Last BD in frame. Coalesce Now – Pass through Send Buffer Descriptor flag. mbuf – – Broadcom ® January 29, 2016 • 5718-PG108-R Page 348...
Page 349: Vlan Tag Register For Tcp Segmentation (Offset: 0Xcf0)
The CPU sets this bit to 1 to inform the SDI that the TCP Segmentation is completed, and the BD_Index can be incremented. Unsupported_Mss Status – Reserved 27:7 – BD Index The internal current buffer descriptor pointer that the hardware/firmware is servicing. Broadcom ® January 29, 2016 • 5718-PG108-R Page 349...
Page 350: Send Data Completion Control Registers
It is same as SDCQ bit 12. Reserved 28:12 – Head TXMBUF pointer 11:6 Head TXMBUF Pointer. They are same as SDCQ bits 11:6. Tail TXMBUF pointer Tail TXMBUF Pointer. They are same as SDCQ bits 5:0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 350...
Page 351: Send Bd Selector Control Registers
Description Reserved 31:3 – Error Send BD Ring Selector error status. Reserved – Send BD Ring Selector Hardware Diagnostics Register (offset: 0x1408) Default Name Bits Access Value Description Reserved 31:0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 351...
Page 352: Send Bd Ring Selector Local Nic Send Bd Consumer Index Register (Offset: 0X1440-0X147C)
Send BD 14 Consumer Index RO. 0x1478-0x147b Send BD Ring Selector Local NIC Send BD 15 Consumer Index RO. 0x147c-0x147f Send BD Ring Selector Local NIC Send BD 16 Consumer Index RO. Broadcom ® January 29, 2016 • 5718-PG108-R Page 352...
Page 353: Send Bd Initiator Control Registers
This is a self clearing bit. Send BD Initiator Status Register (offset: 0x1804) Default Name Bits Access Value Description Reserved 31:3 – Error Send BD Initiator Error. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 353...
Page 354: Send Bd Diagnostic Initiator Local Nic Bd N Producer Index Registers (Offset: 0X1808-0X1844)
Send BD 12 Producer Index RO. 0x1838-0x183b Send BD 13 Producer Index RO. 0x183c-0x183f Send BD 14 Producer Index RO. 0x1840-0x1843 Send BD 15 Producer Index RO. 0x1844-0x1847 Send BD 16 Producer Index RO. Broadcom ® January 29, 2016 • 5718-PG108-R Page 354...
Page 355: Send Bd Fetch Threshold Register (Offset: 0X1850)
IOV Mode Only 0x31C 0x5998 0x3F18 0x318 0x599C 0x3F1C 0x324 0x59A0 0x3F20 0x320 0x59A4 0x3F24 0x32C 0x59A8 0x3F28 0x328 0x59AC 0x3F2C 0x334 0x59B0 0x3F30 0x330 0x59B4 0x3F34 0x33C 0x59B8 0x3F38 0x338 0x59BC 0x3F3C Broadcom ® January 29, 2016 • 5718-PG108-R Page 355...
Page 356: Send Bd Completion Control Registers
Until it is completely halted, it – remains 1 when read Reset When this is set to 1, the Send BD Completion State machine is reset. This is a self clearing bit – Broadcom ® January 29, 2016 • 5718-PG108-R Page 356...
Page 357: Receive List Placement Registers
Mapping out of Range – Class of service mapping is out of the range of Attention the active queue number. Class Zero Attention – Class field extracted from frame descriptor is zero. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 357...
Page 358: Receive Selector Non-Empty Bits Register (Offset: 0X200C)
2. For example, if the system wants four classes of service and four interrupt distribution lists per class of service, this value is set to four and the Number of Active Lists value is set to 16. Broadcom ® January 29, 2016 • 5718-PG108-R Page 358...
Page 359: Receive List Placement Statistics Control Register (Offset: 0X2014)
Disable MACTQ Double Ack Disable MACTQ double ack issue fix. issue fix 1: Disabled 0: Enabled Reserved 17:2 – Disable ASF Lockup Issue Fix 1 Disable ASF Lockup Fix. 1: Disabled 0: Enabled Broadcom ® January 29, 2016 • 5718-PG108-R Page 359...
Page 360: Receive List Placement Statistics Increment Mask Register (Offset: 0X201C)
Receive Selector List 5 Count Registers (offset: 0x2148) Receive Selector List 6 Count Registers (offset: 0x2158) Receive Selector List 7 Count Registers (offset: 0x2168) Receive Selector List 8 Count Registers (offset: 0x2178) Broadcom ® January 29, 2016 • 5718-PG108-R Page 360...
Page 361 Receive Selector List 13 Count Registers (offset: 0x21c8) Receive Selector List 14 Count Registers (offset: 0x21d8) Receive Selector List 15 Count Registers (offset: 0x21e8) Receive Selector List 16 Count Registers (offset: 0x21f8) Broadcom ® January 29, 2016 • 5718-PG108-R Page 361...
Page 362: Receive Data And Receive Bd Initiator Control Registers
10 => RDI shall wait for a BD to become available in the VRQ's BD cache, no matter how long it takes. 11 => Reserved for future use. Ignored in non-IOV mode Broadcom ® January 29, 2016 • 5718-PG108-R Page 362...
Page 363: Receive Data And Receive Bd Initiator Status Register (Offset: 0X2404)
The received frame size is too big for the into one Receive BD selected Receive BD. Jumbo Frame Enable Enable Jumbo Receive BD is needed and Jumbo Receive BD ring is disabled attention. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 363...
Page 364: Vrq Status Register (Offset: 0X240C)
VRQ flush timer expires. RDI engine will generate a single pulse clear request along with current IOV status [16:0] vector to various modules to clear local maintained index values for that particular IOV process. Broadcom ® January 29, 2016 • 5718-PG108-R Page 364...
Page 365: Vrq Flush Timer Register (Offset: 0X2414)
Name Bits Access Value Description Host Address High 31:0 The host ring address is the host address of the first ring element. The host ring address is in host address format. Broadcom ® January 29, 2016 • 5718-PG108-R Page 365...
Page 366: Jumbo Producer Ring Host Address Low Register (Offset: 0X2444)
Name Bits Access Value Description Host Address High 31:0 The host ring address is the host address of the first ring element. The host ring address is in host address format. Broadcom ® January 29, 2016 • 5718-PG108-R Page 366...
Page 367: Receive Producer Ring Host Address Low Register (Offset: 0X2454)
The local return ring producer index is set to the value placed in the DMA descriptor. The local controller receive return consumer index is also set to the value placed in the DMA descriptor. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 368: Receive Bd Ring Initiator Local Nic Standard Receive Bd Consumer Index (Offset: 0X2474)
B2HRX MCAST PKT 31:0 CORW Host B2HRX multicast packet count. B2HRX Broadcast Statistics Count (offset: 0x24DC) Default Name Bits Access Value Description B2HRX BCAST PKT 31:0 CORW Host B2HRX broadcast packet count. Broadcom ® January 29, 2016 • 5718-PG108-R Page 368...
Page 369: B2Hrx Drop Packet Count (Offset: 0X24E0)
B2HRX MCAST PKT 31:0 CORW APE B2HRX multicast packet count. B2HRX APE Broadcast Statistics Count (offset: 0x24F4) Default Name Bits Access Value Description B2HRX BCAST 31:0 CORW APE B2HRX broadcast packet count. Broadcom ® January 29, 2016 • 5718-PG108-R Page 369...
Page 370: B2Hrx Ape Drop Packet Count (Offset: 0X24F8)
APE B2HRX packet drop count due to empty RBD. B2HRX APE Drop Packet Byte Count (offset: 0x24FC) Default Name Bits Access Value Description B2HRX DROP OCTETS 31:0 CORW APE B2HRX packet drop byte count due to empty RBD. Broadcom ® January 29, 2016 • 5718-PG108-R Page 370...
Page 371: Receive Data Completion Control Registers
Until it is completely halted, it remains one when read. Reset When this bit is set to 1, the Receive Data Completion state machine is reset. This is a self- clearing bit. Broadcom ® January 29, 2016 • 5718-PG108-R Page 371...
Page 372: Receive Bd Initiator Control Registers
Current Jumbo Received BD Index requested by Producer Ring requested RBDI for BD fetching. Notice that, this index is Index different from MB producer index and also different from the index indicated by RBDC. Broadcom ® January 29, 2016 • 5718-PG108-R Page 372...
Page 373: Receive Bd Initiator Local Nic Receive Bd Producer Index Register (Offset: 0X2C0C-0X2C13)
DMA engine to initiate a transfer of buffer descriptors for replenishing the ring. Standard Replenish LWM Register (offset 0x2D00) Default Name Bits Access Value Description Legacy 31:8 Unused Broadcom ® January 29, 2016 • 5718-PG108-R Page 373...
Page 374: Jumbo Replenish Lwm Register (Offset 0X2D04)
(LWM+1), a BD fetch is request triggered. Recommended Settings: • Non-IOV mode: JMB LWM: 16. (1/4 of total RBDs) • IOV mode: JMB LWM: 4. (1/4 of total RBDs) Broadcom ® January 29, 2016 • 5718-PG108-R Page 374...
Page 375: Bd Fetch Limit Register (Offset 0X2D08)
Completion state machine is reset. This is a self- clearing bit. Receive BD Completion Status Register (offset: 0x3004) Default Name Bits Access Value Description Reserved 31:3 – Error Receive BD Completion Error Status. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 375...
Page 376: Nic Jumbo Receive Bd Producer Index Register (Offset: 0X3008)
D0u (this feature is not used in device enters D0u. BCM5718 family) 1: Enable 0: Disable. Reserved 26:22 – Reserved – Reserved – SGMII/PCS Powerdown Setting this bit will powerdown SGMII-PCS module. Broadcom ® January 29, 2016 • 5718-PG108-R Page 376...
Page 377 CPMU Register Software RW SC 0x0 Software reset for resetting all the registers to Reset default. CPMU Software Reset RW SC 0x0 Software reset for all the CPMU logic expect for registers. Broadcom ® January 29, 2016 • 5718-PG108-R Page 377...
Page 378: Link Speed 10 Mb/No Link Power Mode Clock Policy Register (Offset: 0X3604)
10001: Core = 12.5 MHz (CK25/2) 10011: Core = 6.25 MHz (CK25/4) 10101: Core = 3.125 MHz (CK25/8) 10111: Core = 1.563 MHz (CK25/16) 11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2) Reserved 15:0 0x0000 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 378...
Page 379: Link Speed 100 Mb Power Mode Clock Policy Register (Offset: 0X3608)
10011: Core = 6.25 MHz (CK25/4) 10101: Core = 3.125 MHz (CK25/8) 10111: Core = 1.563 MHz (CK25/16) 11001: Core = 781 kHz (CK25/32) 11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2) Reserved 15:0 0x0000 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 379...
Page 380: Link Speed 1000 Mb Power Mode Clock Policy Register (Offset: 0X360C)
10011: Core = 6.25 MHz (CK25/4) 10101: Core = 3.125 MHz (CK25/8) 10111: Core = 1.563 MHz (CK25/16) 11001: Core = 781 kHz (CK25/32) 11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2) Reserved 15:0 0x0000 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 380...
Page 381: Link Aware Power Mode Clock Policy Register (Offset: 0X3610)
00111: 7.5 MHz (Alt Source/16) 01001: 3.75 MHz (Alt Source/32) 10001: 25.0 MHz (CK25) 10011: 12.5 MHz (CK25/2) 10101: 6.25 MHz (CK25/4) 10111: 3.125 MHz (CK25/8) 11001: 1.563 MHz (CK25/16) Reserved 0x0000 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 381...
Page 382: D0U Clock Policy Register (Offset: 0X3614)
10011: Core = 6.25 MHz (CK25/4) 10101: Core = 3.125 MHz (CK25/8) 10111: Core = 1.563 MHz (CK25/16) 11001: Core = 781 kHz (CK25/32) 11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2) Reserved 15:0 0x0000 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 382...
Page 383: Ape Clk Policy Register (Offset: 0X361C)
APE Clock Switch Clock Override. 00000: 62.5 MHz (NCSI DLL/2)10001: 25.0 MHz (CK25) 10011: 12.5 MHz (CK25/2) 10101: 6.25 MHz (CK25/4) 10111: 3.125 MHz (CK25/8) 11001: 1.563 MHz (CK25/16) 11110: 125 MHz Broadcom ® January 29, 2016 • 5718-PG108-R Page 383...
Page 384 Software Controlled APE Clock Speed Select in Link Aware Power mode in BCM5719 10001: 25.0 MHz (CK25) (BCM5717) Reserved 10011: 12.5 MHz (CK25/2) (BCM5718) 10101: 6.25MHz (CK25/4) 10111: 3.125 MHz (CK25/8) 11001: 1.563 MHz (CK25/16) Broadcom ® January 29, 2016 • 5718-PG108-R Page 384...
Page 385: Ape Sleep State Clock Policy Register (Offset: 0X3620)
00101: 15.0 MHz (Alt Source/8) 00111: 7.5 MHz (Alt Source/16) 01001: 3.75 MHz (Alt Source/32) 10001: 25.0 MHz (CK25) 10011: 12.5 MHz (CK25/2) 10101: 6.25 MHz (CK25/4) 10111: 3.125 MHz (CK25/8) 11001: 1.563 MHz (CK25/16) Broadcom ® January 29, 2016 • 5718-PG108-R Page 385...
Page 386: Clock Speed Override Policy Register (Offset: 0X3624)
Reserved 31:14 – MAC Clock Speed Override Enable MAC clock speed override*. Enable 1: Enable 0: Disable APE Clock Speed Override Enable APE clock speed override*. Enable 1: Enable 0: Disable Broadcom ® January 29, 2016 • 5718-PG108-R Page 386...
Page 387: Status Register (Offset: 0X362C)
APE Engine Status 11: Reserved 10: Deep Sleep State 01: Sleep State 00: Active State WOL ACPI Detection Enable – 1: ACPI detection enabled Status of Port 1 0: ACPI detection disabled Broadcom ® January 29, 2016 • 5718-PG108-R Page 387...
Page 388 1: On 0: Off CPMU Power State – Indicates the current power state of the CPMU. Power Management State – Indicates the current state of hardware power Machine State management state machine. Broadcom ® January 29, 2016 • 5718-PG108-R Page 388...
Page 389: Clock Status Register (Offset: 0X3630)
– APE FCLK clock disable status APE HCLK Disable Status – APE HCLK clock disable status Reserved 23:21 – MAC Clock Switch Status 20:16 – MAC Core Clock Speed Select Status Broadcom ® January 29, 2016 • 5718-PG108-R Page 389...
Page 390 Name Bits Access Value Description Reserved 15:13 – APE Clock Switch Status 12:8 – APE Clock Speed Select Status Flash Clock Switch Status – Flash Clock Speed Select Status Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 390...
Page 391: Gphy Control/Status Register (Offset: 0X3638)
GPHY DLL IDDQ state Gphy_iddq_dll_act state GPHY pwrdn CPMU controlled output to GPHY GPHY set_bias_iddq CPMU controlled output to GPHY GPHY force_dll_on CPMU controlled output to GPHY GPHY dll_pwrdn_ok CPMU controlled output to GPHY Broadcom ® January 29, 2016 • 5718-PG108-R Page 391...
Page 392: Ram Control Register (Offset: 0X363C)
Default Name Bits Access Value Description Core RAM Power down Legacy Address: 0x6804:[24] Core RAM power down BD RAM Power down Legacy Address: 0x6804:[24] BD RAM power down Reserved 29:0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 392...
Page 393: Core Idle Detection De-Bounce Control Register (Offset: 0X3648)
10011: Core = 6.25 MHz (CK25/4) x32 10101: Core = 3.125 MHz (CK25/8) x64 10111: Core = 1.563 MHz (CK25/16) x128 11001: Core = 781 kHz (CK25/32), x64 11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2) Broadcom ® January 29, 2016 • 5718-PG108-R Page 393...
Page 394: Pcie Idle Detection De-Bounce Control Register (Offset: 0X364C)
This bit allows the software to control the state of the System Energy_Det signal if the Select_HW_Energy_Det control bit (b12) is 0 1: Drive System Energy_Det high 0: Drive System Energy_Det low Broadcom ® January 29, 2016 • 5718-PG108-R Page 394...
Page 395 CPMU clock frequency is 25 MHz) 10: 512 million CPMU clocks (20 seconds if CPMU clock frequency is 25 MHz) 11: 1024 million CPMU clocks (40 seconds if CPMU clock frequency is 25 MHz) Broadcom ® January 29, 2016 • 5718-PG108-R Page 395...
Page 396: Dll Lock Timer Register (Offset: 0X3654)
Chip ID 27:12 0x5717 – 0x5718 0x5719 Base Layer Revision 11:8 0000 Base layer revision history Information 0000: A0 0001: B0 0010: C0 Metal Layer Revision Metal layer revision history Information Broadcom ® January 29, 2016 • 5718-PG108-R Page 396...
Page 397: Mutex Request Register (Offset: 0X365C)
Default Name Bits Access Value Description Reserved 31:6 Readable and writeable reserved bits. APE CM3 Big Endian Enable 8 Enable APE CM3 Big Endian Setting. Reserved Readable and writeable reserved bits. Broadcom ® January 29, 2016 • 5718-PG108-R Page 397...
Page 398: Padring Control Register (Offset: 0X3668)
1 = Disable 0 = Enable OOB Power Consumption FIX Enable fix for OOB Power Consumption FIX for for 5784 Option 1 5784 option 1. 1 = Enable 0 = Disable Broadcom ® January 29, 2016 • 5718-PG108-R Page 398...
Page 399: Flash Clock Policy Register (Offset: 0X366C)
Flash Idle mode Enable 1: Enable Flash Idle mode 0: Disable Flash Idle mode Force EAV Clock Disable EAV clock Disable 1: Disable EAV clock 0: Enable EAV clock Reserved 27:20 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 399...
Page 400 Software Controlled Flash Clock Speed Select000: 62.5 MHz (NCSI DLL) 010: 25 MHz (CK25) Reserved – Override Flash Clock Switch Software Controlled Flash Clock Speed Select000: 62.5 MHz (NCSI DLL) 010: 25 MHz (CK25) Broadcom ® January 29, 2016 • 5718-PG108-R Page 400...
Page 401: Link Idle Control Register (Offset: 0X3670)
Link idle/Host Access condition control. 1: disable this idle condition when entering link idle mode and host access mode. 0: enable this idle condition when entering link idle mode and host access mode. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 401...
Page 402 Link idle/Host Access condition control. 1: disable this idle condition when entering link idle mode and host access mode. 0: enable this idle condition when entering link idle mode and host access mode. Broadcom ® January 29, 2016 • 5718-PG108-R Page 402...
Page 403 Link idle/Host Access condition control. 1: disable this idle condition when entering link idle mode and host access mode. 0: enable this idle condition when entering link idle mode and host access mode. Broadcom ® January 29, 2016 • 5718-PG108-R Page 403...
Page 404: Link Idle Status Register (Offset: 0X3674)
— TXAMAC Idle — RXER = 0 — RXDV = 0 — MDIO Idle — FTQ empty — GRC Idle — MBUF empty — MA Idle — No core reset — Broadcom ® January 29, 2016 • 5718-PG108-R Page 404...
Page 405: Top Level Miscellaneous Control 1 Register (Offset: 0X367C)
47147 fix disable–PCIe MDIO reset fix disable. 1–Disable 0–Enable 47173 fix disable 47173 fix disable–CLKREQ_L tri-state fix disable. 1–Disable 0–Enable Debug UART Port Selection Select the Debug UART Port. 00: port0 01: port1 10: port2 11: port3 Broadcom ® January 29, 2016 • 5718-PG108-R Page 405...
Page 406: Miscellaneous Control Register (Offset: 0X36Ac)
13.217 µs with no delay 10 MB/s 1518byte packet–advances l1aspm exiting by 1274.94 µs with no delay 10 MB/s 64byte packet–advances l1aspm exiting by 113.98 µs with no delay Reserved 15:0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 406...
Page 407: Eee Mode Register (Offset: 0X36B0)
PCIE early L1 exit debounce timer in us. Timer Default is 63 µs. EEE Link Idle Debounce Timer 15:0 0x3F EEE link idle debounce timer in us. Default is 63 µs. Broadcom ® January 29, 2016 • 5718-PG108-R Page 407...
Page 408: Eee Debounce Timer 2 Control Register (Offset: 0X36B8)
LAN TX Packet Buffer Empty LAN core internal packet buffer status control. 1: disable this idle condition from the EEE idle detection logic. 0: enable this idle condition in the EEE idle detection logic. Broadcom ® January 29, 2016 • 5718-PG108-R Page 408...
Page 409: Eee Link Idle Status Register (Offset: 0X36C0)
EEE Link Idle Entering Counter 31:0 This counter counts the number of timers the debounced version of EEE link idle is asserted. The entire 32 bit register can be cleared by writing 0xFFFFFFFF. Broadcom ® January 29, 2016 • 5718-PG108-R Page 409...
Page 410: Eee Control Register (Offset: 0X36D0)
Current Measurement Lower 32-bit Read Register = 2s Hold Count[31:0] 0x3: Current Measurement Upper 32-bit Read Register = 2s Average Count[63:32] Current Measurement Lower 32-bit Read Register = 2s Average Count [31:0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 410...
Page 411: Current Measurement Upper 32-Bit Read Register (Offset: 0X36D8)
1 as long as the request is pending. Writing a 0 to a bit shall have no effect. Reading this field may return zero or more bits with value 1–each bit with value 1 indicates a pending request. Broadcom ® January 29, 2016 • 5718-PG108-R Page 411...
Page 412: Global Mutex Grant Register (Offset: 0X36F4)
31:19 – Temperature Monitor Power Temperature Monitor Power Down Down Temperature Monitor Hold Temperature Monitor Hold Temperature Data 16:8 Temperature Data Bias Adjust Bias Adjust ADC Test Enable ADC Test Enable Broadcom ® January 29, 2016 • 5718-PG108-R Page 412...
Page 413: Host Coalescing Control Registers
Until it is completely halted, it remains one when read. Reset – When this bit is set to 1, the Host Coalescing state machine is reset. This is a self-clearing bit. Broadcom ® January 29, 2016 • 5718-PG108-R Page 413...
Page 414: Host Coalescing Status Register (Offset: 0X3C04)
Receive Coalescing Ticks Register for VRQ 6 => 0x3DF8 Receive Coalescing Ticks Register for VRQ 7 => 0x3E10 Receive Coalescing Ticks Register for VRQ 8 => 0x3E28 Receive Coalescing Ticks Register for VRQ 9 => 0x3E40 Broadcom ® January 29, 2016 • 5718-PG108-R Page 414...
Page 415: Send Coalescing Ticks Register (Offset: 0X3C0C)
This will generally increase performance in hosts that do not require their send buffers to be freed quickly. For host environments that do require their send buffers to be recovered quickly, it is recommended that this register be set to 0. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 416: Receive Max Coalesced Bd Count Register (Offset: 0X3C10)
For simplicity, if a host wanted to get a status block update for every received packet, the host driver should just set this register to a value of 1. On the other hand, by setting the value in this register to a high Broadcom ®...
Page 417 Receive Max Coalesced BD Count Register for VRQ 14 => 0x3EC0 Receive Max Coalesced BD Count Register for VRQ 15 => 0x3ED8 Receive Max Coalesced BD Count Register for VRQ 16 => 0x3EF0 Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 418: Send Max Coalesced Bd Count Register (Offset: 0X3C14)
Send Max Coalesced BD Count Register for TXQ 14 => 0x3EC4 Send Max Coalesced BD Count Register for TXQ 15 => 0x3EDC Send Max Coalesced BD Count Register for TXQ 16 => 0x3EF4 Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 419: Receive Max Coalesced Bd Count During Interrupt Register (Offset: 0X3C18)
MailBox register and thus the interrupt is in a masked state. If this parameter triggers (while in During Interrupt state), the chip will DMA the latest Status Block to the host memory, but the interrupt will remain deasserted. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 420 Send Max Coalesced BD Count During Interrupt Register for TXQ 14 => 0x3ECC Send Max Coalesced BD Count During Interrupt Register for TXQ 15 => 0x3EE4 Send Max Coalesced BD Count During Interrupt Register for TXQ 16 => 0x3EFC Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 421: Hc Parameter Set Reset Register (Offset: 0X3C28)
Status Block 12 Host Address Register (offset: 0x3D58) Status Block 13 Host Address Register (offset: 0x3D60) Status Block 14 Host Address Register (offset: 0x3D68) Status Block 15 Host Address Register (offset: 0x3D70) Broadcom ® January 29, 2016 • 5718-PG108-R Page 421...
Page 422: Status Block Base Address Register (Offset: 0X3C44)
RCB Incorrectly Configured – Set if one of the RCBs is incorrectly configured based on the whole configuration. DMA Completion Discard – The DMA Completion Discard state machine has caused an attention. Broadcom ® January 29, 2016 • 5718-PG108-R Page 422...
Page 423: Nic Jumbo Receive Bd Consumer Index Register (Offset: 0X3C50-0X3C58)
WDMA module before be DMAed in status block. NIC Jumbo Receive BD Consumer Index Register (offset: 0x3C50) Default Name Bits Access Value Description Received BD jumbo Producer Current Received BD Consumer index. Ring consumer Index Broadcom ® January 29, 2016 • 5718-PG108-R Page 423...
Page 424: Nic Standard Receive Bd Consumer Index Register (Offset: 0X3C54)
This register contains the Receive Return Ring 1 Producer Index. Default Name Bits Access Value Description Reserved 31:9 – NIC Return Ring Producer – NIC Return Ring 1 Producer Index. Index Broadcom ® January 29, 2016 • 5718-PG108-R Page 424...
Page 425: Nic Diagnostic Return Ring 2 Producer Index Register (Offset: 0X3C88)
Host Coalescing engine to the host). It is shared between the Send BD Initiator and the Host Coalescing state machines. Default Name Bits Access Value Description Reserved 31:9 – NIC Send BD Consumer Index 8:0 – NIC Send BD Consumer Index. Broadcom ® January 29, 2016 • 5718-PG108-R Page 425...
Page 426: Memory Arbiter Control Registers
DMAW1 Addr Trap Enable DMA Write 1 Memory Arbiter request trap enable. RX-MAC Addr Trap Enable Receive MAC Memory Arbiter request trap enable. TX-MAC Addr Trap Enable Transmit MAC Memory Arbiter request trap enable. Broadcom ® January 29, 2016 • 5718-PG108-R Page 426...
Page 427: Memory Arbiter Status Register (Offset: 0X4004)
DMA Read 1 Memory Arbiter request trap. DMAW1 Addr Trap DMA Write 1 Memory Arbiter request trap. RX-MAC Addr Trap Receive MAC Memory Arbiter request trap. TX-MAC Addr Trap Transmit MAC Memory Arbiter request trap. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 427...
Page 428: Memory Arbiter Trap Address Low Register (Offset: 0X4008)
RXMBUF base. It will also cause the RXMAC to drop the preallocated MBUF and request a new one. MBUF Low Attn Enable MBUF Low Attn Enable MBUF low attention enable. Broadcom ® January 29, 2016 • 5718-PG108-R Page 428...
Page 429: Buffer Manager Status Register (Offset: 0X4404)
22:0 0xA000h Specifies beginning of the MBUF for receive packet. The base address will ignore the lower seven bits, thus aligning the beginning of the MBUF pool on a 128-byte boundary. Broadcom ® January 29, 2016 • 5718-PG108-R Page 429...
Page 430: Mbuf Pool Length Register (Offset: 0X440C)
Set this bit to 1 to request for the MBUF. When this bit is read as 0, then read the MBUF allocation Response register for the TXMBUF pointer. Reserved 30:0 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 430...
Page 431: Rx Risc Mbuf Allocation Response Register (Offset: 0X4420)
This 32-bit register provides debug information on the RXMBUF pointer. Default Name Bits Access Value Description Reserved 31:25 – Next RXMBUF Deallocation 24:16 The next RXMBUF that is to be deallocated. pointer Reserved 15:9 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 431...
Page 432: Receive Flow Threshold Register (Offset: 0X4458)
Receive Flow Threshold Register (offset: 0x4458) Default Name Bits Access Value Description Reserved 31:9 – MBUF Threshold Defines the integer number of MBUFs remaining before the receive MAC will drop received frames. Broadcom ® January 29, 2016 • 5718-PG108-R Page 432...
Page 433: Rdma Registers
1: Disable Multiple Outstanding Read DMA This bit will always read back as 0, even if written as 1. This feature should be disabled in 5718 A0 Chip Reserved 23:18 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 433...
Page 434 Until it is completely halted, it remains one when read. Reset When this bit is set to 1, the Read DMA state machine is reset. This is a self-clearing bit. Broadcom ® January 29, 2016 • 5718-PG108-R Page 434...
Page 435: Lso Read Dma Status Register (Offset: 0X4804)
[7:0]. Reserved 29:16 – Programmable Extension 15:8 These bits contain the programmable extension Header Type #2 header value for programmable header #2. Broadcom ® January 29, 2016 • 5718-PG108-R Page 435...
Page 436: Lso Read Dma Reserved Control Register (Offset: 0X4900)
XOFF state under heavy bi-directional netperf traffic when flow control is enabled. Fifo_threshold_mbuf_req 23:16 0x30 – MBUF Threshold MBUF 15:8 0x54 – Request Broadcom ® January 29, 2016 • 5718-PG108-R Page 436...
Page 437: Lso/Non-Lso/Bd Read Dma Corruption Enable Control Register (Offset: 0X4910)
The two bits define the burst length that the Non- Non-LSO RDMA engine LSO RDMA read engine would request to the PCI block. • 00 = 128B • 01 = 256B • 10 = 512B • 11 = 4KB Broadcom ® January 29, 2016 • 5718-PG108-R Page 437...
Page 438 Tx Read DMA lock-up issue. Note that increasing the ASPM L1 entry time to a value on the order of 1ms is recommended and may prevent this issue from occurring. See register 0x7d28. Broadcom ® January 29, 2016 • 5718-PG108-R Page 438...
Page 439 Note that increasing the ASPM L1 entry time to a value on the order of 1ms is recommended and may prevent this issue from occurring. See register 0x7d28. Reserved – Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 439...
Page 440: Bd Read Dma Mode Register (Offset: 0X4A00)
(PCI read longer than DMA length.) Read DMA PCI FIFO Underrun Enable Read DMA PCI FIFO Underrun Attention. Attention Enable Read DMA PCI FIFO Overrun Enable Read DMA PCI FIFO Overrun Attention. Attention Enable Broadcom ® January 29, 2016 • 5718-PG108-R Page 440...
Page 441: Bd Read Dma Status Register (Offset: 0X4A04)
0xYYYYYYYY_00000000 in a single read). This is a fatal error. Read DMA PCI Parity Error Read DMA PCI Parity Error. Read DMA PCI Master Abort Read DMA PCI Master Abort Error. Broadcom ® January 29, 2016 • 5718-PG108-R Page 441...
Page 442: Bd Read Dma Reserved Control Register (Offset: 0X4A70)
Name Bits Access Value Description Fifo_threshold_bd_req 31:24 – Fifo_threshold_mbuf_req 23:16 0x30 – MBUF Threshold MBUF 15:8 0x54 – Request Reserved – Clock Request Fix Enable – MBUF Threshold Clk Req – Broadcom ® January 29, 2016 • 5718-PG108-R Page 442...
Page 443: Bd Read Dma Corruption Enable Control Register (Offset: 0X4A78)
This bit has no effect on Post-DMA processing of IPv4 packets. Hardware IPv4 Post-DMA Enables hardware processing of LSO IPv4 Processing Enable packets. This bit has no effect on Post-DMA processing of IPv6 packets. Broadcom ® January 29, 2016 • 5718-PG108-R Page 443...
Page 444 This is a fatal error. Read DMA PCI Parity Error Enable Read DMA PCI Parity Error Attention. Attention Enable Read DMA PCI Master Abort Enable Read DMA PCI Master Abort Attention. Attention Enable Broadcom ® January 29, 2016 • 5718-PG108-R Page 444...
Page 445: Non-Lso Read Dma Status Register (Offset: 0X4B04)
Read DMA PCI Parity Error Read DMA PCI Parity Error. Read DMA PCI Master Abort Read DMA PCI Master Abort Error. Read DMA PCI Target Abort Read DMA PCI Target Abort Error. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 445...
Page 446: Non-Lso Read Dma Programmable Ipv6 Extension Header Register (Offset: 0X4B08)
Access Value Description Host Addr 31:0 Latched host address Host Address for the DMA Read Channel 2 (offset: 0x4B38) Default Name Bits Access Value Description Host Addr 31:0 Latched host address Broadcom ® January 29, 2016 • 5718-PG108-R Page 446...
Page 447: Host Address For The Dma Read Channel 3 (Offset: 0X4B40)
Fifo_threshold_mbuf_req 23:16 0x30 – MBUF Threshold MBUF 15:8 0x54 – Request Reserved – Clock Request Fix Enable – MBUF Threshold Clk Req – Broadcom ® January 29, 2016 • 5718-PG108-R Page 447...
Page 448: Non-Lso Read Dma Corruption Enable Control Register (Offset: 0X4B7C)
Note that increasing the ASPM L1 entry time to a value on the order of 1ms is recommended and may prevent this issue from occurring. See register 0x7d28. Reserved – Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 448...
Page 449: Write Dma Registers
Write DMA PCI FIFO Overwrite Enable Write DMA PCI FIFO Overwrite Attention Attention Enable (PCI write longer than DMA length). Write DMA PCI FIFO Underrun Enable Write DMA PCI FIFO Underrun Attention. Attention Enable Broadcom ® January 29, 2016 • 5718-PG108-R Page 449...
Page 450: Write Dma Status Register (Offset: 0X4C04)
Write DMA PCI Parity Error. Write DMA PCI Master Abort Write DMA PCI Master Abort Error. Error Write DMA PCI Target Abort Write DMA PCI Target Abort Error. Error Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 450...
Page 451: Rx-Cpu Registers
Note: Firmware developers should take care to clear this bit before polling internal SRAM memory locations, because the RX RISC processor uses a two-element LRU caching algorithm, which is not affected by writes from the PCI interface. Broadcom ® January 29, 2016 • 5718-PG108-R Page 451...
Page 452: Rx Risc Status Register (Offset: 0X5004)
MA outstanding write FIFO MA_wr_FIFO overflowed. The RX RISC is halted overflow on this condition. Reserved 26:16 – Instruction fetch stall The processor is currently stalled due to an instruction fetch. Broadcom ® January 29, 2016 • 5718-PG108-R Page 452...
Page 453: Rx Risc Program Counter (Offset: 0X501C)
RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 454: Vrq Statistics
Queue#2 Transmit IFHCOUTBCAST 0x0A2C Queue#2 Transmit IFHCINOCTETS_GOOD 0x0A30 VRQ#2 Receive Reserved 0x0A34 VRQ#2 Receive IFHCINUCASTPKTS 0x0A38 VRQ#2 Receive IFHCINMULTICASTPKTS 0x0A3C VRQ#2 Receive …. ………. …….. – – …. ………. ……... – – Broadcom ® January 29, 2016 • 5718-PG108-R Page 454...
Page 455: Vrq Filter Set Registers
[0 through 31]: (Offset 0x5400–0x547C) • VRQ_FILT_ELEM_PTTRN_REG [0 through 31]: (Offset 0x5480–0x54FC) • VRQ_FILT_SET_MASK_REG [1 through 31]: (Offset 0x5504–0x557C) Note: There is no equivalent of FILT_SET_CFG_REG(s) in VRQ-Filter Block. Also, Set#0 is non- existent. Broadcom ® January 29, 2016 • 5718-PG108-R Page 455...
Page 456: Vrq Mapper Registers
Address Reg for Term A. Table 113: Second Half VRQ Mapper Entry Register Default Name Bits Access Value Description Product Term D Activate Product Term D Write a 1 to activate this whole Product Term. Broadcom ® January 29, 2016 • 5718-PG108-R Page 456...
Page 457: Table 114: Vrq Mapper Register List
Table 114: VRQ Mapper Register List VRQ Entry # Second Half Register Address First Half Register Address 0 (Default) 0x5604 0x5600 0x560C 0x5608 0x5614 0x5610 0x561C 0x5618 0x5624 0x5620 0x562C 0x5628 Broadcom ® January 29, 2016 • 5718-PG108-R Page 457...
Page 458: Vrq Enable Register (Offset 0X560)
Ring Producer RX Return Ring VRQ # Index Index Consumer Index Comments Producer Index 0x270 UNDI – 0x98 UNDI – 0x88 64-bit 0x3C80 Registers (Default) HP – 0x268 HP – 0x280 Broadcom ® January 29, 2016 • 5718-PG108-R Page 458...
Page 459: Perfect Match Destination Address Registers
VRQ_PERFECT_MATCH[4–23]_HIGH_REG (Offsets: 0x5690, 0x5698, 0x56A0 … 0x5728) There are total 24 Perfect (Destination Address) Match registers for VRQ Filtering in RX-MAC. These registers hold the higher 2 octets of the matching address. Broadcom ® January 29, 2016 • 5718-PG108-R Page 459...
Page 460: Vrq_Perfect_Match[4 - 23]_Low_Reg (Offsets: 0X5694, 0X569C, 0X56A4
If it is zero this indicates the host is not in the interrupt handler. The Host Coalescing engine uses this information to determine which set of coalescing parameters it should use. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 461: General Mailbox Registers 1-8 (Offset: 0X5820-0X5824)
The Receive BD Return Ring 1 Consumer Index Register contains the index of the last buffer descriptor for Receive Return Ring 1 that has been consumed. Host software writes this register whenever it updates the return ring 1. This register must be initialized to 0. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 462: Receive Bd Return Ring 2 Consumer Index Register (Offset: 0X5890-0X5897)
Send BD Ring Host Producer Index Register for Ring 13 (offset: 0x5934) Send BD Ring Host Producer Index Register for Ring 14 (offset: 0x5938) Send BD Ring Host Producer Index Register for Ring 15 (offset: 0x593C) Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 463: Send Bd Ring Nic Producer Index Register (Offset: 0X5980)
Send BD Ring Producer Index Register for Ring 15 (offset: 0x59B8) Send BD Ring Producer Index Register for Ring 16 (offset: 0x59BC) Flow Through Queues All registers reset are core reset unless specified. Broadcom ® January 29, 2016 • 5718-PG108-R Page 463...
Page 464: Ftq Reset Register (Offset: 0X5C00)
Reset DMA High Priority Read Set this bit to reset the DMA High Priority Read flow through queue. When set to 0, this flow through queue is ready for use. This bit is self- clearing. Broadcom ® January 29, 2016 • 5718-PG108-R Page 464...
Page 465: Mac Tx Fifo Enqueue Register (Offset: 0X5Cb8)
When the Valid bit is 1 and the Pass bit is 0, the CPU can take the RXMBUF cluster pointers to access the received Packet. • When the CPU writes a 1 to the Skip bit, the hardware will pop the head of the queue entry. Broadcom ® January 29, 2016 • 5718-PG108-R Page 465...
Page 466: Message Signaled Interrupt Registers
This register exists only for testing purposes and should always be programmed to zero. (BCM5718) Reserved – (BCM5719) MSIX Multimode – Vector Enable MSI Byte Swap – Broadcom ® January 29, 2016 • 5718-PG108-R Page 466...
Page 467: Msi Status Register (Offset: 0X6004)
Writing this bit with a value of one will cause the request to be asserted. Writing this bit with a value of 0 has no effect. Broadcom ® January 29, 2016 • 5718-PG108-R Page 467...
Page 468: Dma Completion Registers
Cause a host interrupt when an enabled flow attention occurs. Interrupt on DMA Attention Cause a host interrupt when an enabled DMA attention occurs. Interrupt on MAC Attention Cause a host interrupt when an enabled MAC attention occurs. Broadcom ® January 29, 2016 • 5718-PG108-R Page 468...
Page 469 The RX MAC forwards illegal frames to the NIC and marks them as such instead of discarding them. The frames are queued based on default class and interrupt distribution queue number. NO_CRC – Broadcom ® January 29, 2016 • 5718-PG108-R Page 469...
Page 470: Miscellaneous Configuration Register (Offset: 0X6804)
Miscellaneous Configuration Register (offset: 0x6804) Default Name Bits Access Value Description Bond ID 7 Bond ID 6 Disable GRC Reset on PCIE Setting this bit will prevent reset to PCIE block. block Bond ID 5 Broadcom ® January 29, 2016 • 5718-PG108-R Page 470...
Page 471: Miscellaneous Local Control Register (Offset: 0X6808)
When set, the PME Status bit in the PMSCR register is forced high. If PME Enable is also set, the PME signal will activate. This register bit is write-only and self-clearing after write. Reserved – Broadcom ® January 29, 2016 • 5718-PG108-R Page 471...
Page 472 Clear Interrupt bit in the Miscellaneous Host Control register. This bit is not operational in MSI mode. Interrupt State This bit reflects the state of the PCI INTA pin. This bit is not operational in MSI mode. Broadcom ® January 29, 2016 • 5718-PG108-R Page 472...
Page 473: Timer Register (Offset: 0X680C)
Receive Data and Receive BD Initiator FTQ has stalled. SW Event 5 SW Event 5 is set Recv BD Comp Receive BD Completion FTQ has stalled. SW Event 4 SW Event 4 is set Broadcom ® January 29, 2016 • 5718-PG108-R Page 473...
Page 474: Rx-Cpu Timer Reference Register (Offset: 0X6814)
0 followed by a read. Exit the loop when the read returns nonzero. To release the semaphore, Default Name Bits Access Value Description Reserved 31:1 – RX-CPU Semaphore RX-CPU Semaphore Broadcom ® January 29, 2016 • 5718-PG108-R Page 474...
Page 475: Serial Eeprom Address Register
HC Module – RX CPU Module – EMAC Module – Memory Map Enable Bit Set by hardware, cleared by software. Reserved – High Priority Mailbox – Low Priority Mailbox – – Broadcom ® January 29, 2016 • 5718-PG108-R Page 475...
Page 476 RDIQ FTQ (Received an ASF) 8 – ASF Location 12 – Reserved – ASF Location 11 – Reserved – ASF Location 10 – Reserved – ASF Location 9 – ASF Location 8 – Broadcom ® January 29, 2016 • 5718-PG108-R Page 476...
Page 477: Miscellaneous Control Registers
1 boot code in RX MBUF. These bits behave identical to bit 31 in that they have no effect on state machine operation and they are cleared only by a power-on reset. Broadcom ® January 29, 2016 • 5718-PG108-R Page 477...
Page 478: Power Management Debug Register (Offset: 0X68A4)
PCIE PLL Fast Acquisition Select. 0: Disable Fast Acquisition 1: Enable Fast Acquisition irxSeqStart PCIE RX Sequence Start ipllSeqStart PCIE PLL Sequence Start irxpowerdown RX Power Down Status itxpowerdown TX Power Down Status Broadcom ® January 29, 2016 • 5718-PG108-R Page 478...
Page 479: 5755Me Miscellaneous Control Register (Offset: 0X68B0)
TM control for APE ARB. APE ATB mem tm TM control for APE ATB. APE shared mem tmb TMb control for APE shared mem. APE shared mem tma TMa control for APE shared mem. Broadcom ® January 29, 2016 • 5718-PG108-R Page 479...
Page 480: Mem Tm Control 3(Offset: 0X68E8)
13:12 RW 0x00 TM control for Ch1 non-LSO RDMA engine memory. FIFO tma control Non-LSO Ch0 RDMA 11:10 RW 0x00 TM control for Ch0 non-LSO RDMA engine memory. FIFO tmb control Broadcom ® January 29, 2016 • 5718-PG108-R Page 480...
Page 481: Tph Hint Register (Offset: 0X68Fc)
Resvd – PH Value 10:9 – TH Enable – Send BD Read Resvd – PH Value – TH Enable – Packet Data Read Resvd – PH Value – TH Enable – Broadcom ® January 29, 2016 • 5718-PG108-R Page 481...
Page 482: Eav Ref Count Capture Lsb Reg (Offset: 0X6900)
Note: Hardware behavior shall be indeterminate in case of conflicting or duplicate assignment of GPIO pins to the same resource. A platform MUST allocate its dedicated TimeSync_GPIO pin first before using any pin from APE_GPIO shared pool. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 483: Eav Ref Count Snapshot Lsb[0] Reg (Offset 0X6910)
This LSB & MSB pair captures the EAV Reference Count when externally triggered by the desired TimeSync/ APE_GPIO pin–a toggle serves a trigger. The only legal sequence of accessing this pair is Read-LSB followed by Read-MSB. Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 484: Eav Ref Count Snapshot Msb[0] Reg (Offset: 0X6914)
TX Time Watchdog LSB[1] Reg (offset: 0x6920) Default Name Bits Access Value Description Watchdog LSB Value 31:0 0x0000 “TX Time Watchdog MSB[1] Reg (offset: 0x6924)” on page 485. Broadcom ® January 29, 2016 • 5718-PG108-R Page 484...
Page 485: Tx Time Watchdog Msb[1] Reg (Offset: 0X6924)
APE_GPIO pin; a toggle serves a trigger. The only legal sequence of accessing this pair is Read-LSB followed by Read-MSB. Default Name Bits Access Value Description EAV Reference Count 31:0 LSB of the EAV Reference Count as snapshot by Snap-shot TimeSync/APE_GPIO. [lower half] [2:0] shall always be 000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 485...
Page 486: Eav Ref Count Snapshot Msb[1] Reg [Offset 0X6934]
EAV Ref Count Snapshot MSB[1] Reg [Offset 0x6934] Default Name Bits Access Value Description EAV Reference Count 31:0 MSB of the EAV Reference Count as snap-shot by Snap-shot TimeSync/APE_GPIO. [Upper half] Broadcom ® January 29, 2016 • 5718-PG108-R Page 486...
Page 487: Non-Volatile Memory (Nvm) Interface Registers
This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set Erase The erase command bit. Set high to execute an erase. This bit is ignored if the wr is clear. Broadcom ® January 29, 2016 • 5718-PG108-R Page 487...
Page 488: Nvm Write Register (Offset: 0X7008)
The 24 bit address for a read or write operation (must be 4 byte aligned). NVM Read Register (offset: 0x7010) Default Name Bits Access Value Description Read Data 31:0 32bits of read data are used when read commands are executed. Broadcom ® January 29, 2016 • 5718-PG108-R Page 488...
Page 489: Nvm Config 1 Register (Offset: 0X7014)
0 means that an SCK transitions at a minimum of each CORE_CLK rising edge. The equation to calculate the clock freq. for SCK CORE_CLK / ((SPI_CLK_DIV + 1) * 2) Broadcom ® January 29, 2016 • 5718-PG108-R Page 489...
Page 490: Nvm Config 2 Register (Offset: 0X7018)
0x81 if pin strap = This is the Flash page erase command. Atmel Note: ST25xx does not support page erase, 0xDB if pin strap = therefore the corresponding command is for STMxx sector erase. Broadcom ® January 29, 2016 • 5718-PG108-R Page 490...
Page 491: Nvm Config 3 Register (Offset: 0X701C)
Write 1 to clear REQ5 bit. REQ_SET5 Write 1 to set REQ5 bit. REQ4 Software request bit 4. 1 in this bit indicates that the request4 is active. ARB_WON4 Arbitration won bit 4(see bit 8, ARB_WON0) Broadcom ® January 29, 2016 • 5718-PG108-R Page 491...
Page 492 Write 1 to this bit to set REQ2 bit. REQ_SET1 Write 1 to this bit to set REQ1 bit. REQ_SET0 Set software arbitration request bit 0. This bit is set by writing 1. Broadcom ® January 29, 2016 • 5718-PG108-R Page 492...
Page 493: Nvm Access Register (Offset: 0X7024)
This command will be issued by the flash interface state machine through SPI interface. To flash device, and make the flash device write- enabled. Arbitration Watchdog Timer Register (offset: 0x702C). Broadcom ® January 29, 2016 • 5718-PG108-R Page 493...
Page 494: Arbitration Watchdog Timer Register (Offset: 0X702C)
Auto Config Successful Auto config is successful. Auto Config Enable Auto config feature is enabled through pin strap. Reserved–Auto_conf_states The auto-sense FSM state. Auto_config_busy 1: auto-config FSM is busy 0: auto-config is complete Broadcom ® January 29, 2016 • 5718-PG108-R Page 494...
Page 495: Section 14: Transceiver Registers
GPHY 0x04 SERDES 0x08 SERDES 0x09 SERDES 0x0A SERDES 0x0B Table 122: BCM5720 Port 0 Port 1 Block PHY Address Block PHY Address GPHY 0x01 GPHY 0x02 SERDES 0x08 SERDES 0x09 Broadcom ® January 29, 2016 • 5718-PG108-R Page 495...
Page 496: Register Field Access Type
CR = clear on read Transceiver Register Map Address Name MII_Control_Register MII_Status_Register PHY_Identifier_MSB_Register PHY_Identifier_LSB_Register Auto_Negot_Advertisement_Register Auto_Negot_Link_Partner_Ability_Base_Pg_Register Auto_Negot_Expansion_Register Auto_Negot_Next_Page_Transmit_Register Auto_Negot_Link_Partner_Ability_Nxt_Pg_Register 1000Base_T_Control_Register 1000Base_T_Status_Register 0Bh–0Eh Reserved_by_IEEE IEEE_Extended_Status_Register PHY_Extended_Control_Register PHY_Extended_Status_Register Receive_Error_Counter_Register False_Carrier_Sense_Counter_Register Local_Remote_Rcvr_NOT_OK_Counters_Register DSP_Coefficient_Read_Write_Port_Register DSP_Control_Register DSP_Coefficient_Address_Register Broadcom ® January 29, 2016 • 5718-PG108-R Page 496...
Page 497 001 => 10 BASE-T 010 => Power Control 011 => IP Phone 100 => Misc Test 101 => Misc Test 2 110 => Manual IP Phone seed 111 => Misc Control Auxiliary_Status_Register Interrupt_Status_Register Interrupt_Mask_Register Broadcom ® January 29, 2016 • 5718-PG108-R Page 497...
Page 498 11011 => Auxiliary 1000X Control 11100 => Auxiliary 1000X Status 11101 => Misc 1000X Status 11110 => Auto-Detect Medium 11111 => Mode Control Master_Slave_Seed_Register Shadow Register: 1 => HCD Status Test1_Register Test2_Register Broadcom ® January 29, 2016 • 5718-PG108-R Page 498...
Page 499: Figure 54: Copper Phy Register Mapping Table
1Ah – Interrupt Status Reg 1Bh – Interrupt Mask Reg 1Ch – Shadow Regs (bits [14:10] = Shadow Selector) [14:10] = 0 – Cabletron LED Reg [14:10] = 1Fh – Mode Control Reg Broadcom ® January 29, 2016 • 5718-PG108-R Page 499...
Page 500: 00H-0Fh 10/100/1000T Register Map Detailed Description
UNIDIRECTIONAL_ENABLE RW When 0.12=0 AND 0.8=1: 1 = able to transmit packets when no link 0 = requires link in order to transmit packets RESERVED 000000 write as 0, ignore on read Broadcom ® January 29, 2016 • 5718-PG108-R Page 500...
Page 501: 01H: Mii_Status_Register
0 = link fail JABBER_DETECT 1 = jabber condition detected 0 = no jabber condition detected EXTENDED_CAPABILITY RO H 1 1 = extended register capabilities supported 0 = basic register set capabilities only Broadcom ® January 29, 2016 • 5718-PG108-R Page 501...
Page 502: 02H: Phy_Identifier_Msb_Register
0 = not 100BASE-TX full duplex capable 100BASETX_HALF_ RW 1 1 = 100BASE-TX capable DUPLEX_CAPABLE 0 = not 100BASE-TX capable 10BASET_FULL_DUPLE RW 1 1 = 10BASE-T full duplex capable X_CAPABLE 0 = not 10BASE-T full duplex capable Broadcom ® January 29, 2016 • 5718-PG108-R Page 502...
Page 503: 05H: Auto_Negot_Link_Partner_Ability_Base_Pg_Register
(see IEEE spec for encoding) * RW when “writeable link partner ability test mode” (reg 1Fh bit 10) is set 06h: Auto_Negot_Expansion_Register Name Default Description 15:7 RESERVED 000h ignore on read Broadcom ® January 29, 2016 • 5718-PG108-R Page 503...
Page 504: 07H: Auto_Negot_Next_Page_Transmit_Register (Software Controlled Next
Message code field or unformatted code field 08h: Auto_Negot_Link_Partner_Ability_Nxt_Pg_Register Name Default Description NEXT_PG 1 = additional next pages will follow 0 = sending last page ACKNOWLEDGE3 1 = acknowledge 0 = no acknowledge Broadcom ® January 29, 2016 • 5718-PG108-R Page 504...
Page 505: 09H: 1000Base_T_Control_Register
0 = Advertise not 1000BASE-T half duplex capable RESERVED RW 00000000 write as 0, ignore on read # Registers updated with pin defaults on rising edge of restart autoneg pin (tied to gnd at top level). Broadcom ® January 29, 2016 • 5718-PG108-R Page 505...
Page 506: 0Ah: 1000Base_T_Status_Register
0 = IEEE Registers are currently accessible 0Fh: IEEE_Extended_Status_Register Name Default Description 1000BASE_X_FULL_DUPLEX_ RO L 0 1 = 1000BASE-X full duplex capable CAPABLE 0 = not 1000BASE-X full duplex capable Broadcom ® January 29, 2016 • 5718-PG108-R Page 506...
Page 507 0 = not 1000BASE-T full duplex capable 1000BASE_T_HALF_DUPLEX_ RO H 1 1 = 1000BASE-T half duplex capable CAPABLE 0 = not 1000BASE-T half duplex capable 11:0 RESERVED 000h ignore on read Broadcom ® January 29, 2016 • 5718-PG108-R Page 507...
Page 508: 10H-1Fh Register Map Detailed Description
0 = LED traffic mode disabled FORCE_LEDS_ON 1 = force all LED’s into “ON” state 0 = normal LED operation FORCE_LEDS_OFF 1 = force all LED’s into “OFF” state 0 = normal LED operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 508...
Page 509: 11H: Phy_Extended_Status_Register (Copper Side Only)
RO LL 0 1 = remote receiver status OK 0 = remote receiver status not OK LOCAL_RECEIVER_STATUS RO LL 0 1 = local receiver status OK 0 = local receiver status not OK Broadcom ® January 29, 2016 • 5718-PG108-R Page 509...
Page 510: 12H: Receive_Error_Counter_Register
RW CR 0000h Number of non-collision packets with receive errors since last read. Freezes at FFFFh. (Counts SerDes errors when register 1ch shadow “11011” bit 9 = 1 otherwise copper errors) Broadcom ® January 29, 2016 • 5718-PG108-R Page 510...
Page 511: 13H: False_Carrier_Sense_Counter_Register
0 = allow normal length Ethernet packets only 13:12 EDGERATE CONTROL 00 = 4.0ns (1000T) (1000T) 01 = 5.0ns (1000T) (LSB or’ed with ER pin) 10 = 3.0ns (1000T) 11 = 0.0ns (1000T) Broadcom ® January 29, 2016 • 5718-PG108-R Page 511...
Page 512 111 = Misc Control register Writes to the selected shadow register are done on a single cycle (no setup required). Reads are selected by first writing to register 18h, shadow 7, bits 14:12. Broadcom ® January 29, 2016 • 5718-PG108-R Page 512...
Page 513: 18H: 10Base-T Register (Shadow Register Selector = "001")
POLARITY ERROR 1 = channel polarity inverted 0 = channel polarity correct BLOCK RXDV 1 = block rxdv for 4 additional rxc cycles for ipg EXTENSION (IPG) 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 513...
Page 514 SHADOW REGISTER Writes to the selected shadow register are SELECTOR done on a single cycle (no setup required). Reads are selected by first writing to register 18h, shadow 7, bits 14:12. Broadcom ® January 29, 2016 • 5718-PG108-R Page 514...
Page 515: 18H: Power/Mii Control Register (Shadow Register Selector = "010")
EXTENDED LINK PULSE 1 = enable extended link pulse width WIDTH ENABLE transmission 0 = normal operation ENABLE IP PHONE 1 = IP Phone detection enabled DETECTION 0 = IP Phone detection disabled Broadcom ® January 29, 2016 • 5718-PG108-R Page 515...
Page 516: 18H: Misc Test Register 1 (Shadow Register Selector = "100")
ADC10BT, PC10BT, CRS10BT, DAC10_100 test modes use tpin10; register value ignored). BLOCK 10BT RESTART 1 = prevent 10BT from restarting auto- AUTO-NEGOTIATION negotiation in order to break the link 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 516...
Page 517: 18H: Misc Test Register 2 (Shadow Register Selector = "101")
See reg 18-2.15:13 11:10 ENC error scale 00 = no scaling 01 = scaled by 0.5 10 = scaled by 0.25 others: no scaling SPARE write as 0, ignore on read Broadcom ® January 29, 2016 • 5718-PG108-R Page 517...
Page 518 Writes to the selected shadow register are done SELECTOR on a single cycle (no setup required). (REFERENCE ONLY) Reads are selected by first writing to register 18h, shadow 7, bits 14:12. Broadcom ® January 29, 2016 • 5718-PG108-R Page 518...
Page 519: 18H: Manual Ip Phone Seed Register (Shadow Register Selector = "110")
RGMII TIMING MODE 1 = clock delayed 90 degrees (output delay only) 0 = clock and data aligned RGMII MODE 1 = use reduced GMII mode 0 = normal GMII/MII operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 519...
Page 520: 19H: Auxiliary Status Summary (Copper Side Only)
000 = no highest common denominator (when auto-neg complete = 1) or auto-negotiation not complete (when auto-neg complete = 0) PARALLEL DETECTION 1 = parallel detection fault FAULT 0 = no parallel detection fault Broadcom ® January 29, 2016 • 5718-PG108-R Page 520...
Page 521: 1Ah: Interrupt Status Register (Copper Side Only)
0 = all counters below 128 AUTO-NEG. PAGE RX 1 = page received since last read 0 = interrupt cleared HCD NO LINK 1 = negotiated HCD did not establish link 0 = interrupt cleared Broadcom ® January 29, 2016 • 5718-PG108-R Page 521...
Page 522: 1Bh: Interrupt Mask Register
1Bh: Interrupt Mask Register Name Description Default 15:0 INTERRUPT MASK 1 = interrupt masked (status bits still operate FFFFh VECTOR normally but do not generate interrupt output) 0 = interrupt enabled Broadcom ® January 29, 2016 • 5718-PG108-R Page 522...
Page 523: 1Ch: Cabletron Led Register (Shadow Register Selector = "00H")
Shadow Register Selector 00000 SELECTOR 00000 = shadow register 0 read/write select 00001 = shadow register 1 read/write select 11111 = shadow register 31 read/write select RESERVED Write as 0, ignore on read Broadcom ® January 29, 2016 • 5718-PG108-R Page 523...
Page 524: 1Ch: Dll Selection Register (Shadow Register Selector = "01H")
2. test mode selection is from slice1. 1Ch: Spare Control 1 Register (Shadow Register Selector = “02h”) Name Description Default WRITE ENABLE 1 = write bits [9:0] 0 = read bits [9:0] Broadcom ® January 29, 2016 • 5718-PG108-R Page 524...
Page 525: 1Ch: Clock Alignment Control Register (Shadow Register Selector = "03H")
Delay value is latched into selected GMII clock STROBE delay line on rising edge of this bit. RXCLK ALIGNMENT Delay value is latched into selected RX clock STROBE delay line on rising edge of this bit. Broadcom ® January 29, 2016 • 5718-PG108-R Page 525...
Page 526: 1Ch: Spare Control 2 Register (Shadow Register Selector = "04H")
1 = internally disable phya2 input (consult Testability document for suggested usage). enable rbc0/1 & txc/rxc tri 1 = enable tristating of rbc0/1 or txc/rxc sate 0 = rbc0/1 & txc/rxc not tristated. Broadcom ® January 29, 2016 • 5718-PG108-R Page 526...
Page 527: 1Ch: Spare Control 3 Register (Shadow Register Selector = "05H")
0 = Sigdet Deassert Timer =1 us AUTO-POWER DOWN 1 = disable powering down of the dll during auto- DLL OFF DISABLE power down. 0 = enable powering down of dll during auto- power down. Broadcom ® January 29, 2016 • 5718-PG108-R Page 527...
Page 528: 1Ch: Tdr Control 1 Register
0: disable fext mode MASTER 1: master mode 0: slave mode EXTERNAL PHY NO 1: tdr test with external phy without auto- AUTO-NEG negotiation 0: tdr test with external phy with auto- negotiation Broadcom ® January 29, 2016 • 5718-PG108-R Page 528...
Page 529: 1Ch: Led Status Register (Shadow Register Selector = "08H")
See description for bit 4 below. SPARE write as 0, ignore on read external_serdes_inuse 1= drive transmit led low when external SerDes led mode is selected, inactive when not selected 0= normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 529...
Page 530: 1Ch: Sgmii Slave Register (Shadow Register Selector = "15H")
(when set in SGMII or GBIC mode, then both copper and SerDes link must be valid). 0 = link down SERDES DUPLEX 1 = SerDes full-duplex 0 = SerDes half-duplex or auto-negotiating in progress Broadcom ® January 29, 2016 • 5718-PG108-R Page 530...
Page 531 1 = enable SGMII slave auto-detection. 00000 DETECTION Switch between 1000-X and SGMII slave (register 1c shadow 1fh modes based on SerDes received auto- negotiation code word. bit [2] must be 0) 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 531...
Page 532: 1Ch: Misc 1000-X Control 2 Register (Shadow Register Selector = "16H")
0 = write bits [5:0] when bit [15] is also set during a write cycle On Reads: 1 = “SerDes link” (reg 1ch shadow 15h[9] = 1) and “remote_copper_mode” ([9] of this register = 1) Broadcom ® January 29, 2016 • 5718-PG108-R Page 532...
Page 533: 1Ch: Misc 1000-X Control Register (Shadow Register Selector = "17H")
1Ch: Misc 1000-X Control Register (Shadow Register Selector = “17h”) Name Description Default WRITE ENABLE 1 = write bits [9:0] 0 = read bits [9:0] 14:10 SHADOW REGISTER Shadow Register Selector 10111 SELECTOR Broadcom ® January 29, 2016 • 5718-PG108-R Page 533...
Page 534 FIBER SUPER-ISOLATE RW 1 = Fiber super-isolate DISABLE 1000-X 1 = disable1000-X power-down from POWERDOWN auto-medium detection and fiber auto-power down. (register 0 power-down not affected) 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 534...
Page 535: 1Ch: Auto-Detect Sgmii/Gbic Register (Shadow Register Selector = "18H")
01 = support 10k byte packets (1000T PCS transmit FIFO 00 = support 5k byte packets (w/200 ppm offset) in SGMII/GBIC mode: MSB is located at expansion reg 46[15] from SerDes to copper link partner) Broadcom ® January 29, 2016 • 5718-PG108-R Page 535...
Page 536: 1Ch: Test 1000-X Register (Shadow Register Selector = "19H")
1 = force TXFIFO to be always active in 1000X (dig1000x_tx_fifo) 0 = normal operation towards SerDes link partner BYPASS PCS RECEIVE 1 = bypass pcs receive 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 536...
Page 537: 1Ch: Autoneg 1000-X Debug Register (Shadow Register Selector = "1Ah")
0 = error state has not been entered since last read SYNC_STATUS FAILED 1 = sync_status failed since last read (reg 1ch shadow 27 [3] = 0) 0 = sync_status has not failed since last read Broadcom ® January 29, 2016 • 5718-PG108-R Page 537...
Page 538: 1Ch: Auxiliary 1000-X Control Register (Shadow Register Selector = "1Bh")
1 = enable autoneg error timer (error state TIMER ENABLE entered when error timer expires in ability_detect, acknowledge_detect, or idle_detect state) 0 = normal operation COMMA DETECT 1 = enable comma detection ENABLE 0 = disable comma detection Broadcom ® January 29, 2016 • 5718-PG108-R Page 538...
Page 539: 1Ch: Auxiliary 1000-X Status Register (Shadow Register Selector = "1Ch")
0 = link status change has not occurred since last read SGMII SELECTOR 1 = SGMII selector mismatch in SGMII mode MISMATCH 0 = Fiber, copper, GBIC mode, or SGMII selector does not mismatch, or autoneg disabled Broadcom ® January 29, 2016 • 5718-PG108-R Page 539...
Page 540 0 = link is down for SerDes applications PAUSE RESOLUTION– 1 = enable pause receive RECEIVE SIDE 0 = disable pause receive PAUSE RESOLUTION– 1 = enable pause transmit TRANSMIT SIDE 0 = disable pause transmit Broadcom ® January 29, 2016 • 5718-PG108-R Page 540...
Page 541: 1Ch: Misc 1000-X Status Register (Shadow Register Selector = "1Dh")
0 = no carrier extend error since last read EARLY END 1 = early end extension since last read EXTENSION (early_end_ext state in pcs receive) DETECTED 0 = no early end extension since last read Broadcom ® January 29, 2016 • 5718-PG108-R Page 541...
Page 542: 1Ch: Auto-Detect Medium Register (Shadow Register Selector = "1Eh")
1 = fiber selected when both medium active MEDIUM PRIORITY 0 = copper selected when both medium active AUTO-DETECT 1 = enable auto-detect medium MEDIUM ENABLE (switch between GMII/RGMII->copper or GMII/RGMII->fiber) 0 = disable auto-detect medium Broadcom ® January 29, 2016 • 5718-PG108-R Page 542...
Page 543: 1Ch: Mode Control Register (Shadow Register Selector = "1Fh")
1Dh: Master/Slave Seed Register (Bit 15 = 0) Name Description Default ENABLE SHADOW 1 = select shadow register REGISTER 0 = normal operation Writes to the selected register are done on a single cycle (no setup required). Broadcom ® January 29, 2016 • 5718-PG108-R Page 543...
Page 544: 1Dh: Hcd Status Register (Bit 15 = 1)
* HCD 1000T 1 = Gigabit half-duplex hcd occurred since last read 0 = hcd cleared * HCD 100T FDX 1 = 100tx full-duplex hcd occurred since last read 0 = hcd cleared Broadcom ® January 29, 2016 • 5718-PG108-R Page 544...
Page 545: 1Eh: Test1_Register
(errors will only be counted after this bit is set!) 0 = normal operation COUNTER TEST MODE RW 1 = forces counters into test mode 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 545...
Page 546: 1Fh: Test2_Register
000 = ARB 001 = RX1000 010 = RX 011 = TX1000 100 = TX 101 = BASET LINK TEST AUTO-NEG TIMER RW 1 = auto-negotiation timer test mode 0 = normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 546...
Page 547: Serdes Phy Register Definitions
The PHY registers are broken into two blocks: • Block 0 is for IEEE and non-IEEE controls. • Blocks 0, 2 and 3 are non-IEEE blocks, where the analog section or the SerDes is controlled. Broadcom ® January 29, 2016 • 5718-PG108-R Page 547...
Page 548: Register Map
Analog transmitter output for the SerDes when it is in FX (Fiber) mode. ANALOG_RX1 Controlling the SerDes receiver ANALOG_RX2 100FX Test Mode ANALOG_PLL Controlling the GE PLL circuitry BLOCKADDRESS Block address register Broadcom ® January 29, 2016 • 5718-PG108-R Page 548...
Page 549: Figure 55: Serdes Phy Register Map
12h – ANALOG_TXAMP Reg Analog Defined MII Registers Registers 13h – ANALOG RX1 Reg Block Address 3 14h – ANALOG_RX2 Reg 10h to 1Fh Analog Defined 15h – ANALOG PLL Reg Broadcom ® January 29, 2016 • 5718-PG108-R Page 549...
Page 550: Mii Control
Bit[1] of manual Speed[1:0] in SGMII mode only. This field is ignored in 1000Base-X operation. 1X = 1000 Mbps 01 = 100 Mbps 00 = 10 Mbps RESERVED Reserved write 0, ignore read. Broadcom ® January 29, 2016 • 5718-PG108-R Page 550...
Page 551: Mii Status
0 = Incapable of AN. 1 = AN capable. LINK_STATUS Link status. 0 = Link fail. 1 = Good link. JABBER_DETECT Jabber detect 0 = Not detected 1 = Jabber detected Broadcom ® January 29, 2016 • 5718-PG108-R Page 551...
Page 552: Autonegadv
Reserved write 0, ignore read PAUSE Pause 2’b00 = No pause 2’b01 = Asymmetric pause 2’b10 = Asymmetric pause towards link partner 2’b11 = Both symmetric and asymmetric pause, towards local device Broadcom ® January 29, 2016 • 5718-PG108-R Page 552...
Page 553: Autoneg Link Partner Ability
1 = Advertise half-duplex Full-duplex 0 = Do not advertise full-duplex 1 = Advertise full-duplex RESERVED Reserved write 0, ignore read. SGMII SGMII mode 0 = Fiber mode 1 = SGMII mode Broadcom ® January 29, 2016 • 5718-PG108-R Page 553...
Page 554: Autonegexpansion
0 = 1000Base-T full duplex not capable. 1 = 1000Base-T full duplex capable. 1000BASET_HDX 0 = 1000Base-T half duplex not capable. 1 = 1000Base-T half duplex capable. 11:0 RESERVED Reserved write 0, ignore read. 0x000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 554...
Page 555: 1000Xcontrol1
[12] = Register 0.8 [11] = Register 0.6 [10] = Register 0.13 [9:0] = “0000000001” To disable the link, set register 0.11 = 1. To enable the link, set register 0.11 = 0. Broadcom ® January 29, 2016 • 5718-PG108-R Page 555...
Page 556: 1000Xcontrol2
1 = Enable 16-stage 10-bit idle transmit test sequence to SerDes transmitter. TX_PKT_SEQ_TEST Stage 1-4, 13-16 = idle. Stage 5-12 = data packet. 0 = Normal operation. 1 = Enable 16-stage 10-bit idle transmit test sequence to SerDes transmitter. Broadcom ® January 29, 2016 • 5718-PG108-R Page 556...
Page 557 1 = Enable parallel detection. (This will turn auto-negotiation on and off as needed to properly link up with the link partner. The idles and auto-negotiation code words received from the link partner are used to make this decision) Broadcom ® January 29, 2016 • 5718-PG108-R Page 557...
Page 558: 1000Xcontrol3
1 = Bypass transmit FIFO in Gigabit mode. (Useful for fiber or Gigabit only applications where the MAC is using the pll_clk125 as the clk_in port. User must meet timing to the pll_clk125 domain) Broadcom ® January 29, 2016 • 5718-PG108-R Page 558...
Page 559: 1000Xstatus1
1 = Receive FIFO error detected since last read. 0 = No receive FIFO error detected since last read. FALSE_CARRIER_DE 1 = False carrier detected since last read. TECTED 0 = No false carrier detected since last read. Broadcom ® January 29, 2016 • 5718-PG108-R Page 559...
Page 560: 1000Xstatus2
Note: When the ten bit interface is selected with fiber mode (1000-X), then link will always be down SGMII_MODE 1 = SGMII mode 0 = Fiber mode (1000-X) 1000XSTATUS2 Register Description: 1000X Status2 Register. Register Offset: 0x15 at Block 0 Broadcom ® January 29, 2016 • 5718-PG108-R Page 560...
Page 561: 1000Xstatus3
0 = An_enable state has not been entered since last read. 1000XSTATUS3 Register Description: 1000X Status3 Register. Register Offset: 0x16 at Block 0 Table 139: 1000XSTATUS3 Bits Name Description Default 15:11 RESERVED Reserved 0x00 Broadcom ® January 29, 2016 • 5718-PG108-R Page 561...
Page 562: Fxcontrol1
Register Offset: 0x10 at Block 2 Table 140: FXCONTROL1 Bits Name Description Default RESERVED Reserved FIBER_AUTOPWRDWN_WAKE 1 = Wake up for 250ms before powering down 0 = Wake up for 42ms before powering down Broadcom ® January 29, 2016 • 5718-PG108-R Page 562...
Page 563: Fxcontrol2
Register Offset: 0x11 at Block 2 Table 141: FXCONTROL2 Bits Name Description Default 15:1 RESERVED Reserved 0x000 EXTEND_PKT_SIZE 1 = Allow reception of extended length packets 0 = Allow normal length Ethernet packets only Broadcom ® January 29, 2016 • 5718-PG108-R Page 563...
Page 564: Fxcontrol3
0 = 100-FX mode link status has not changed since last read FX100_BAD_ESD_DETECTED RO/LH 1 = 100-FX mode bad ESD error detected since last read (premature end) 0 = No 100-FX mode bad ESD error detected since last read Broadcom ® January 29, 2016 • 5718-PG108-R Page 564...
Page 565: Analog_Tx1
Reserved for factory use only. 1 = Select RX clock 0 = Do not select RX clock REG_EDGE_SEL Reserved for factory use only. 1 = Capture on rising edge 0 = Capture on falling edge Broadcom ® January 29, 2016 • 5718-PG108-R Page 565...
Page 566: Analog_Tx2
Register Offset: 0x12 at Block 3 Table 146: ANALOG_TXAMP Bits Name Description Default DRIVER_FULL_RANG Reserved for factory use only. 1 = Enable TX driver full output range 0 = Disable TX driver full output range Broadcom ® January 29, 2016 • 5718-PG108-R Page 566...
Page 567: Table 146: Analog_Txamp
This is to control the output driving amplitude. This is set in conjunction with the DRIVER_CURRENT. DRIVER_CURRENT Setting the output amplitude of the SerDes ranging from 700 mV to 1280 mV. RESERVED Reserved. Broadcom ® January 29, 2016 • 5718-PG108-R Page 567...
Page 568: Analog_Rx1
1 = Use rising edge of rx_wclk 0 = Use falling edge of rx_wclk RESERVED Reserved 0x00 IDDQ Set to power down analog receiver block 1 = Power down RX 0 = Normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 568...
Page 569: Analog_Rx2
Register Description: Controlling the GE PLL circuitry. Register Offset: 0x18 at Block 3 Table 149: ANALOG_PLL Bits Name Description Default 15:1 RESERVED Reserved 0x4040 PLL_POWER_DOWN RW 1 = PLL power down 0 = Normal operation Broadcom ® January 29, 2016 • 5718-PG108-R Page 569...
Page 570: Ge_Prbs_Control
In PRBS mode, this bit indicates signal is no longer available or PRBS pattern is loss. Lock In PRBS mode, this indicates PRBS pattern is locked. 10:0 Prbs_errors In PRBS mode, this indicates number of errors detected. 0x0000 Broadcom ® January 29, 2016 • 5718-PG108-R Page 570...
Page 571: Clause 45 Registers
0x7); //Set function field to address and device to 0x7 phy_write(0xe, 0x3C); //Write 3Ch to to select the EEE advertise Register phy_write(0xd, 0x4007); //Set function field to data and device to 0x7 Broadcom ® January 29, 2016 • 5718-PG108-R...
Page 572: Clause 45 Register Dev 7 Reg3Ch (60D): Eee Advertisement Register
Clause 45 Register Dev 7 Reg803Eh (32830d): EEE Resolution Status Table 154: Clause 45 Register Dev 7 Reg803Eh: EEE Resolution Status Name Description Default 15:3 Reserved Write as 0, ignore on read Broadcom ® January 29, 2016 • 5718-PG108-R Page 572...
Page 573: Eee 1000Base-T Resolution
Write as 0, ignore on read. Reserved Write as 0, ignore on read. 11:0 Reserved Write as 0, ignore on read. 0000h LPI Feature Enable Setting this bit high enables LPI Broadcom ® January 29, 2016 • 5718-PG108-R Page 573...
Page 574: Appendix A: Flow Control
– Full-duplex connection at Gigabit speed. – Implements flow control. – Flow control enabled. • Switch – Does not drop packets. – Full-duplex connection to Client. • Server – Gigabit connection. Broadcom ® January 29, 2016 • 5718-PG108-R Page 574...
Page 575: File Transfer
Client PCI bus lack bandwidth to DMA packets, at wire speed, to host memory. The user may be playing a DVD, for example. Figure 57: File Transfer Scenario: Speed Mismatch Pause packets Switch Gigabit Server Gigabit Client Broadcom ® January 29, 2016 • 5718-PG108-R Page 575...
Page 576: Switch Buffers Run Low
• Jamming (half-duplex) • Pause frames (full-duplex) Figure 58: File Transfer Scenario: Speed Buffers Run Low Port buffers & memory almost exhausted Client Egres Ingres Server Port Port MAC Sublayer Switch Broadcom ® January 29, 2016 • 5718-PG108-R Page 576...
Page 577: Switch Backpressure
Server’s pause interval to expire. Either way, the Switch no longer will inhibit the Server from sending packets. Figure 60: File Transfer Scenario: Switch Flow Control Pause packets Switch Gigabit Server Gigabit Client Empty Buffered Frames Broadcom ® January 29, 2016 • 5718-PG108-R Page 577...
Page 578: File Transfer Complete
MAC control parameters 00 10 2 bytes Pause frame opcode 42 bytes Reserved field 00 00 00 ... Pause frame opcode 64 bytes - 20 bytes - Delay 10 Quanta (Slot times) mac_ctrl_parm_len Broadcom ® January 29, 2016 • 5718-PG108-R Page 578...
Page 579: Appendix B: Terminology
Send Data Initiator The hardware block updates the DMAs in the packet buffers from host memory. The packet buffers are DMAed after the BD has been moved to device local memory. Broadcom ® January 29, 2016 • 5718-PG108-R Page 579...
Page 580: Appendix C: Device Register And Memory Map
176B 0x00003FFF 0x01003FFF 0x00003FFF 0x00003FFF Unmapped 32KB 0x01004000- 0x01004000- 0x00004000- 0x00004000- 0x0100FFFF 0x0100FFFF 0x0000FFFF 0x0000FFFF RX MBUF 32KB 0x00010000- 0x01010000- 0x00010000- 0x00010000- 0x00019FFF 0x01019FFF 0x00019FFF 0x00019FFF (Relocated or expanded in BCM5717/BCM5718) Broadcom ® January 29, 2016 • 5718-PG108-R Page 580...
Page 581 Access 0xC009FFF 0xC0039FFF 0xC0039FFF 0xC0039FFF Send RCB0 NIC 0x00004000- 0x01004000- 0x00004000- 0x00004000- Address 0x0000400F 0x0100400F 0x0000400F 0x0000400F Receive Standard 0x00040000- 0x01040000- 0x00040000- 0x00040000- Producer RCB0 NIC 0x0004000F 0x0104000F 0x0004000F 0x0004000F Address Broadcom ® January 29, 2016 • 5718-PG108-R Page 581...
Page 582 Table 157: BCM5717 / BCM5718 Memory Map (Cont.) Host Standard Host UNDI Region Size NIC CPU View Host Flat View View (Offset) View Receive Jumbo 0x00044400- 0x01044400- 0x00044400- 0x00044400- Producer RCB0 NIC 0x0004440F 0x0104440F 0x0004440F 0x0004440F Address Broadcom ® January 29, 2016 • 5718-PG108-R Page 582...
Page 583: Bcm5717 / Bcm5718 Register Map
Receive BD Initiator 0x2C1C–0x2FFF Unused RBDC 0x3000–0x33FF 0x3000–0x300F Receive BD Completion 0x3010–0x33FF Unused CMPU 0x3400–0x37FF 0x3400–0x35FF Unused 0x3600–0x3687 Central Power Management Unit 0x3800–0x3BFF 0x3800–0x3817 Debug Unit (UART) 0x3900–0x3907 Chip Debug 0x3908–0x3BFF Unused Broadcom ® January 29, 2016 • 5718-PG108-R Page 583...
Page 584 0x7820–0x7BFF Unused TL-DL-PL Port 0x7C00–0x7FFF 0x7C00–0x7FFF PCIe Core Private Register Access to TL, DL & PL Registers below are outside Host Standard View 0x10000–0x18FFF – APE Access 0x19000–0x193FF – Management Filters Broadcom ® January 29, 2016 • 5718-PG108-R Page 584...
Page 585: Bcm5719 Memory Map
0x01024000– 0x00024000– 0x00024000– Cache 0x000283FF 0x010283FF 0x000283FF 0x000283FF Jumbo RBD 17KB 0x00028400– 0x01028400– 0x00028400– 0x00028400– Cache 0x0002C7FF 0x0102C7FF 0x0002C7FF 0x0002C7FF TX MBUF 29KB 0x0002C800– 0x0102C800– 0x0002C800– 0x0002C800– 0x00033BFF 0x01033BFF 0x00033BFF 0x00033BFF Broadcom ® January 29, 2016 • 5718-PG108-R Page 585...
Page 586 0x0100400F 0x0000400F 0x0000400F Receive Standard 0x00040000- 0x01040000- 0x00040000- 0x00040000- Producer RCB0 0x0004000F 0x0104000F 0x0004000F 0x0004000F NIC Address Receive Jumbo 0x00044400- 0x01044400- 0x00044400- 0x00044400- Producer RCB0 0x0004440F 0x0104440F 0x0004440F 0x0004440F NIC Address Broadcom ® January 29, 2016 • 5718-PG108-R Page 586...
Page 587: Bcm5719 Register Map
Receive BD Initiator 0x2C1C–0x2FFF Unused RBDC 0x3000–0x33FF 0x3000–0x300F Receive BD Completion 0x3010–0x33FF Unused CMPU 0x3400–0x37FF 0x3400–0x35FF Unused 0x3600–0x3687 Central Power Management Unit 0x3800–0x3BFF 0x3800–0x3817 Debug Unit (UART) 0x3900–0x3907 Chip Debug 0x3908–0x3BFF Unused Broadcom ® January 29, 2016 • 5718-PG108-R Page 587...
Page 588 0x7820–0x7BFF Unused TL-DL-PL Port 0x7C00–0x7FFF 0x7C00–0x7FFF PCIe Core Private Register Access to TL, DL & PL Registers below are outside Host Standard View 0x10000–0x18FFF – APE Access 0x19000–0x193FF – Management Filters Broadcom ® January 29, 2016 • 5718-PG108-R Page 588...
Page 589: Bcm5720 Memory Map
0x00020000- 0x00020000- 0x00020000- 0x00023FFF 0x00023FFF 0x00023FFF 0x00023FFF Std RBD Cache 17KB 0x00024000- 0x01024000- 0x00024000- 0x00024000- 0x000283FF 0x010283FF 0x000283FF 0x000283FF Jumbo RBD 17KB 0x00028400- 0x01028400- 0x00028400- 0x00028400- Cache 0x0002C7FF 0x0102C7FF 0x0002C7FF 0x0002C7FF Broadcom ® January 29, 2016 • 5718-PG108-R Page 589...
Page 590: Bcm5720 Register Map
Block Range Sub-Block Range Description HP Mail Box 0x0000 – 0x01FF 0x0000 – 0x01FF Unused {Legacy – PCIe Configuration Register Shadow} 0x0200 – 0x03FF 0x0200 – 0x03FF High Priority Mail Boxes Broadcom ® January 29, 2016 • 5718-PG108-R Page 590...
Page 591 Host Coalescing 0x3CC4 – 0x3FFF MultiQueue HC 0x4000 – 0x43FF 0x4000 – 0x400F Memory Arbiter 0x4010 – 0x43FF Unused 0x4400 – 0x47FF 0x4400 – 0x445B Buffer manager 0x445C – 0x47FF Unused Broadcom ® January 29, 2016 • 5718-PG108-R Page 591...
Page 592 0x7C00 – 0x7FFF PCIe Core Private Register Access to TL, DL & PL The registers below are outside Host Standard View. 0x10000 – 0x18FFF – APE Access 0x19000 – 0x193FF – Management Filters Broadcom ® January 29, 2016 • 5718-PG108-R Page 592...
Page 593 Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

About this Document

Technical Support

Section 1: Introduction

Product Features

Revision Levels

Programming the Ethernet Controllers

Section 2: Hardware Architecture

Theory of Operation

Overview of Features

Receive Data Path

Transmit Data Path

DMA Read

DMA Write

LED Control

Memory Arbiter

Host Coalescing

PHY Control

10Bt/100Btx/1000Base-T Transceiver

Section 3: NVRAM Configuration

Overview

Self-Boot

Section 4: Common Data Structures

Theory of Operation

Descriptor Rings

Status Block

Section 5: Receive Data Flow

Introduction

Receive Producer Ring

Receive Return Rings

Checksum Calculation

VLAN Tag Strip

RX Data Flow Diagram

Receive Side Scaling

Section 6: Transmit Data Flow

Introduction

Send Rings

Checksum Offload

Large Segment Offload

Jumbo Frames

Scatter/Gather

VLAN Tag Insertion

TX Data Flow Diagram

Reset

MAC Address Setup/Configuration

Packet Filtering

Section 7: Device Control

Initialization Procedure

Device Reset Procedure

Device Closing Procedure

Energy Efficient Ethernet

Section 8: IEEE1588

IEEE1588 Time Sync Introduction

Netxtreme Time Sync Assist

Hardware Description

EAV Reference Corrector

Transmit Time Stamping Service

Receive Time Stamp and Sequence ID Registers

Time Sync Registers

Section 9: PCI

Configuration Space

Bus Interface

Expansion ROM

Power Management

Endian Control (Byte and Word Swapping)

Quick Links

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Summary of Contents for Broadcom NetXtreme/NetLink BCM5718 Series