Dma Completion Registers; Dma Completion Mode Register (Offset: 0X6400); Grc Registers; Mode Control Register (Offset: 0X6800) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

DMA Completion Registers

All registers reset are core reset unless specified.

DMA Completion Mode Register (offset: 0x6400)

Name
Reserved
Enable
Reset

GRC Registers

All registers reset are core reset unless specified.

Mode Control Register (offset: 0x6800)

Name
Pcie TL/DL/PL mapping bit
Multicast enable
Pcie TL/DL/PL mapping bit
Interrupt on Flow Attention
Interrupt on DMA Attention
Interrupt on MAC Attention
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:2 RW –
1 RW 0
0 RW 0
Default
Bits Access Value
31 RW 0
30 RW 0
29 RW –
28 RW 0
27 RW 0
26 RW 0
Description
Reserved
This bit controls whether the DMA Completion
state machine is active or not. When set to '0' it
completes the current operation and cleanly
halts. Until it is completely halted it remains '1'
when read.
When this bit is set to '1' the DMA Completion
state machine is reset. This is a self-clearing bit.
Description
Bit[31][22][29] remap PCIE core TL/DL/PL
register to GRC space from 0x6400 to 0x67ff.
[31]:
• 0: Select lower 1 KB of each TL/DL/PL
• 1 Select higher 1 KB of each TL/DL/Pl
[22][29]:
• 00: select TL register
• 01: select DL register
• 10: select PL register
Multicast enable bit.
–
Cause a host interrupt when an enabled flow
attention occurs.
Cause a host interrupt when an enabled DMA
attention occurs.
Cause a host interrupt when an enabled MAC
attention occurs.
DMA Completion Registers
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