Pci State Register (Offset: 0X70) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

PCI State Register (offset: 0x70)

This register is reset by PCIE Reset.
Name
Reserved
Generate reset plus
APE Program Space Write
Enable
APE Shared Memory Write
Enable
APE Control Register Write
Enable
Config Retry
Reserved
Max PCI Target Retry
Flat View
VPD Available
PCI Expansion ROM Retry
PCI Expansion ROM Desired 5
Reserved
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
31:20 RO 0x0000
19 W1 0
Read 0
18 RW 0
17 RW 0
16 RW 0
15 RO 0x1
On Hard
reset
14:12 RO 0x0
11:9 RW 0x1
8 RW 0x0
7 RO 0x0
6 RW 0x0
RW 0x0
4:0 RO XXX
Description
–
For func 1 write 1 generates 10 clock wide reset
pulse reads always 0 for func 0 reserved
When this bit is set the APE program space may
be written.
When this bit is set the APE shared memory
region may be written.
When this bit is set the APE control registers may
be written.
When asserted, forces all config access to be
retried.
–
Indicates the number of PCI clock cycles before
Retry occurs, in multiple of 8. At reset, this field is
set to 001 N/A in PCIE
Asserted if the Base Address register presents a
32 MB PCI Address map flat view, otherwise,
indicates a 64 KB PCI Address map in standard
view
This bit reads as 1 if the VPD region of the
NVRAM can be accessed by the host
Comes from GRC 6808
Force PCI Retry for accesses to Expansion ROM
region if enabled
Enable PCI ROM base address register to be
visible to the PCI host
–
PCI Configuration Registers
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