Lso Read Dma Reserved Control Register (Offset: 0X4900); Lso Read Dma Flow Reserved Control Register (Offset: 0X4904) - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Name
Programmable Extension
Header Type #1

LSO Read DMA Reserved Control Register (offset: 0x4900)

Name
FIX for controller stop passing
traffic
Fix in A1 for Rx discard counter
update in offset x2250 when
multicast/unicast/broadcast
packets are dropped
FIFO High Mark
FIFO Low Mark
Slow Clock Fix Disable
Fix for the DMA FIFO overrun 2
Late Collision Fix Enable
Select FED Enable

LSO Read DMA Flow Reserved Control Register (offset: 0x4904)

Name
Fix for frequent TX time out.
Fifo_threshold_mbuf_req
MBUF Threshold MBUF
Request
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
7:0 RW 0
Default
Bits Access Value
31:21 RW 0
20 RW 0
19:12 RW 0x90
11:4 RW 0x40
3 RW 0
RW 0
1 RW 0
0 RW 0
Default
Bits Access Value
31:24 RW 0
23:16 RW 0x30
15:8 RW 0x54
Description
These bits contain the programmable extension
header value for programmable header #1.
Description
Fix the controller stop passing traffic when flow
control is enabled. It appears that the chip can
get stuck in a permanent XOFF state under
heavy bi-directional netperf traffic when flow
control is enabled.
0: Enable fix
1: Disable fix
–
–
When cleared, it enables the fix to cover a corner
case in the link idle mode to allow the DMA Read
request to be generated when the core clock is
transitioning from slow to fast Enable hardware
fix 25155.
When set, this bit enables the fix, where a DMA
FIFO overrun occurs if a large number of Rx BDs
are fetched while the Tx MBUF is full and the
Read DMA FIFO is empty.
0: Disable Fix
1: Enable Fix
Ensure only 1 request is generated upon any
condition where the core clock is switching from
slow to fast or vice-versa.
Description
This register contains various controls to
configure hardware fix for the chip getting stuck
in a permanent XOFF state under heavy
bi-directional netperf traffic when flow control is
enabled.
–
–
RDMA Registers
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