Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 472

BCM5718 Programmer's Guide
Name
Auto SEEPROM Access
APE_GPIO IN(6:0)
GPIO(2:0) Output
GPIO(2:0) Output Enable
GPIO(2:0) Input
GPIO(3) Output
GPIO(3) Output Enable
GPIO(3) Input
Reserved
Interrupt on Attention
Set Interrupt
Clear Interrupt
Interrupt State
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Bits Access Value
24 RW 0
23:17 RO APE GPIO
default
setting
16:14 RW 0
13:11 RW 0
10:8 RO 0
7 RW 0
6 RW 0
5 RW 0
4 RO 0
3 RW 0
2 WO 0
1 WO 0
0 RO 0
Description
If set, access to serial EEPROM goes through
the serial EEPROM address and data registers.
Otherwise, serial EEPROM control register
should be used.
APE GPIO Status
Holds the value of APE GPIO (6:0) pins
Outputs which are defined by board level design.
When asserted, the device drives miscellaneous
pin outputs.
Input from bidirectional miscellaneous pin.
GPIO3 Output value.
When set to 1, GPIO3 pin will be enabled as an
output pin.
Input value of GPIO3.
–
If set, the host will be interrupted when any of the
attention bits in the CPU event register are
asserted.
If Interrupt Mailbox 0 contains a nonzero value,
setting this bit does nothing. If Interrupt Mailbox
0 is zero, then setting this bit will cause the
internal unmasked interrupt state to be asserted.
The external interrupt state (INTA pin) will also be
asserted immediately if interrupts are not
masked by the Mask Interrupts bit. If interrupts
are masked, INTA will be asserted once
interrupts are unmasked, so long as interrupts
are not first cleared. This bit is not operational in
MSI mode.
This bit provides the same functionality as the
Clear Interrupt bit in the Miscellaneous Host
Control register. This bit is not operational in MSI
mode.
This bit reflects the state of the PCI INTA pin.
This bit is not operational in MSI mode.
GRC Registers
Page 472