Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual page 272

BCM5718 Programmer's Guide
Name Bits
Reserved 18:16
Reserved 15:11
Interrupt Disable 10
Fast Back-to-back 9
Enable
System Error 8
Enable
Stepping Control 7
Parity Error Enable 6
VGA Palette 5
Snoop
Memory Write and 4
Invalidate
Special Cycles 3
Bus Master 2
Memory Space 1
I/O Space 0
Broadcom
®
January 29, 2016 • 5718-PG108-R
Default
Access Value Description
RO 0x0 These bits are reserved and tied low per the PCIE
specification.
RO 0x00 These bits are reserved and tied low per the PCIE
specification.
RW 0x0 When this bit is set, function is not permitted to generate
IntX interrupt messages (deasserted) regardless of any
internal chip logic. Setting this bit has no effect on the
INT_STATUS bit below. Writing this bit to 0 will un-mask
the interrupt and let it run normally.
RO 0x0 Does not apply to PCIE
RW 0x0 When set, this bit enables the non fatal and fatal errors
detected by the function to be reported to the Root
Complex. The function reports such errors to the Root
Complex if it is enabled to do so either through this bit or
though PCI express specific bits in DCR
RO 0x0 Does not apply to PCIE
RW 0x0 This bit enables the write to the Master data parity error
status bit. If this bit is cleared, the master data parity error
status bit will never be set.
RO 0x0 Does not apply to PCIE
RO 0x0 Does not apply to PCIE
RO 0x0 Does not apply to PCIE
RW 0x0 This bit controls the enabling of the bus master activity by
this device. When low, it disables an Endpoint function
from issuing memory or IO requests. Also disables the
ability to issue MSI messages.
RW 0x0 This bit controls the enabling of the memory space. When
disabled, memory transactions targeting this device return
completion with UR status
RO 0x0 This bit indicates that the device does not support I/O
space access because it is zero and can not be modified.
IO transactions targeting this device return completion
with UR status.
PCI Configuration Registers
Page 272