Figure 42: Pci Base Address Register; Figure 43: Pci Base Address Register Bits Read In Standard Mode - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Base Address
The Ethernet controller 64K memory mapped I/O block is determined by the first programmable bit in the BAR.
When the MAC is configured in standard mode, the mask 0xFFFF0000 identifies the BAR bits, which are
programmable. Bit 16 is the first bit encountered in the scan upward, which is programmable; bits 0–3 are
ignored. Host software will read zero values from bits 4–16.
returned to the OS/BIOS during resource allocation.

Figure 43: PCI Base Address Register Bits Read in Standard Mode

Broadcom
®
January 29, 2016 • 5718-PG108-R

Figure 42: PCI Base Address Register

Binary Weighted Value:
the 1st programmable
bit (ascending) indicates
requested block size.
[31:4]
XXXX XXXX XXXX XXX1 0000 0000 0000
[31:4]
Prefetchable:
0 = Disabled
1 = Enabled
P Type M
[3] [2:1] [0]
Figure 43 shows the BAR register and the bits
Binary Weighted Value:
0x00010000 = 64K
X's are don't cares
0
[3]
Configuration Space
Location:
00 = Anywhere
01 = Below 1 MB
10 = Anywhere in 64-bit Addr Space
11 = Reserved
Memory Space Indicator:
I/O = 1
Memory = 0
Ignored:
Bits 0-3
11 0
[2:1] [0]
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