Architecture; Enable Endian Word Swap And Enable Endian Byte Swap Bits; Table 54: Default Translation (No Swapping) On 64-Bit Pci - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Architecture

The Ethernet controller is internally a big-endian machine, and its internal processors are big-endian devices.
The Ethernet controller stores data internally in big-endian format using a 64-bit memory subsystem.
However, many hosts (e.g., x86 systems) use the little-endian format, and the PCI bus uses the little-endian
format. Therefore the Ethernet controller has a number of byte swapping options that may be configured by
software so that Little or Big Endian hosts can interface as seamlessly as possible with Ethernet controller over
PCI. The Ethernet controller has the following bits that control byte and word swapping:
• Enable Endian Word Swap (bit 3, Miscellaneous Host Control register (offset 0x68 into PCI Config register,
se "Miscellaneous Host Control Register (offset: 0x68)" on page
swapping when accessing the Ethernet controller via the PCI target interface.
• Enable Endian Byte Swap (bit 2, Miscellaneous Host Control register (offset 0x68 into PCI Config register,
see "Miscellaneous Host Control Register (offset: 0x68)" on page
swapping (within a 32-bit word) when accessing the Ethernet controller via the PCI target interface.
• Word Swap Data (bit 5, Mode Control register (offset 0x6800 into the Ethernet controller registers). If 1, this
register enables word swapping of frame data when it comes across the bus.
• Byte Swap Data (bit 4, Mode Control register (offset 0x6800 into the Ethernet controller registers). If 1, this
register enables byte swapping of frame data when it comes across the bus.
• Word Swap Non-Frame Data (bit 2, Mode Control register (offset 0x6800 into the Ethernet controller
registers). If 1, this register enables word swapping of non frame data (i.e., buffer descriptors, statistics,
etc.) when it comes across the bus.
• Byte Swap Non-Frame Data (bit 1, Mode Control register (offset 0x6800 into the Ethernet controller
registers). If 1, this register enables byte swapping of non frame data (i.e., buffer descriptors, statistics, etc.)
when it comes across the bus.
The setting of the above swapping bits will affect the order of how data is represented when it is transferred
across PCI. Since byte swapping is a confusing subject, examples will be shown that reflect how each byte
swapping bit works.

Enable Endian Word Swap and Enable Endian Byte Swap Bits

The Enable Endian Word Swap, and Enable Endian Byte Swap bits affect whether words or bytes are swapped
during target PCI accesses. Thus, these bits affect the byte order when the host is directly reading/writing to
registers or control structures that are physically located on the Ethernet controller. These bits do not affect the
byte ordering of packet data or other structures that are mastered (DMAed) by the Ethernet controller.
When the Ethernet controller is accessed via PCI (which is little endian) as a PCI target, the Ethernet controller
must implicitly map those accesses to internal structures that use a 64-bit Big Endian architecture. In the default
case where no swap bits are set the Ethernet controller maps PCI data to internal structures shown in
and Table 55 on page 195.

Table 54: Default Translation (No Swapping) on 64-Bit PCI

MSB
Internal Byte #
Internal Bit # 63
Broadcom
®
January 29, 2016 • 5718-PG108-R
0 1 2
47
Endian Control (Byte and Word Swapping)
282). If 1, this register enables 32-bit word
282). If 1, this register enables byte
3 4 5
31
Table 54
LSB
6 7
15
Page 194