Fxcontrol1; Table 140: Fxcontrol1 - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
Bits Name
10 LATCH_LINKDOWN
9 SD_FILTER
8 SD_MUX
7 SD_FILTER_CHG
6 SIGNAL_DETECT
5 ANA_SIGNAL_DET
4 ANA_SIGDET_CHG
3:0 RESERVED

FXCONTROL1

Register Description: 100FX enabling control register
Register Offset: 0x10 at Block 2
Bits Name
15 RESERVED
14 FIBER_AUTOPWRDWN_WAKE
UP
Broadcom
®
January 29, 2016 • 5718-PG108-R
Table 139: 1000XSTATUS3 (Cont.)
RW Description
RO 1 = Link has been down since register 0*13h bit [9] has
been written a '1'
0 = Link has not been down since register 0*13h bit [9] has
been written a '1'
RO 1 = Output of signal detect filter is set
0 = Output of signal detect is not set
Note: This signal is used for the PCS synchronization.
When register 0*10h bit [2] is 0, then the output of the filter
will be forced high. This status signal is still valid when
register 0*10h bit [14] is 1. Noise pulses less than 16 ns
wide are still removed when even the filter is disabled.
RO 1 = Output of signal detect filter is set
0 = Output of signal detect is not set
Note: This is the only SD status bit that will be valid when
the SerDes is powered down from register 0.11. This status
signal is the "signal detect" input port when register 0*10h
bit [3] is 0, otherwise it is the "signal detect" input port
inverted.
RO 1 = Signal detect has changed since last read
0 = Signal detect has not changed since last read
Note: The signal detect change is based on a change in bit
[9] of this register
RO Signal detect directly from pin
RO Analog signal detect status bit. This status signal is the
analog signal detect status if register 0*13h bit [0] is set,
otherwise it is the value based on register 0*13h bit [1].
RO 1 = Analog signal detect has changed since last read
0 = Analog signal detect has not changed since last read
Note: The analog signal detect change is based on a
change in bit [5] of this register.
RO Reserved

Table 140: FXCONTROL1

RW Description
RW Reserved
RW 1 = Wake up for 250ms before powering down
0 = Wake up for 42ms before powering down
SerDes PHY Register Definitions
Default
0
0
0
0
0
0
0
0
Default
0
0
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