Bus Interface; Description; Figure 44: Read And Write Channels Of Dma Engine - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide

Bus Interface

Description

The read/write DMA engines both drive the PCIe interface. Typically, each DMA engine alternates bursts to the
PCIe bus, and both interfaces may have outstanding transactions on the PCI bus. The BCM5718 family
architecture identifies two channels—a read DMA channel and a write DMA channel. Each channel corresponds
to the appropriate DMA engine (see
discussed in this section.
Read Channel
The following architectural components are involved in the configuration of the PCI/DMA interface:
• DMA read engine
• DMA write engine
• DMA read FIFO
• DMA write FIFO
• PCIe interface
• PCI state register
• DMA read/write register
Broadcom
®
January 29, 2016 • 5718-PG108-R
Figure 44). The configuration of the DMA engines and the PCI interface is

Figure 44: Read and Write Channels of DMA Engine

DMA Write
Engine
Write FIFO
PCI Interface
DMA Read
Engine
Read FIFO
PCIe Bus
Bus Interface
Write Channel
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