Msi Fifo; Status Block - Broadcom NetXtreme/NetLink BCM5718 Series Programmer's Manual

BCM5718 Programmer's Guide
A host update occurs whenever one of the following criteria is met:
• The number of BDs consumed for frames received, without updating receive indices on the host, is equal to
or has exceeded the threshold set in the Receive_Max_Coalesced_BD register (see
Coalesced Bd Count Register (Offset: 0x3c10)" on page
• The number of BDs consumed for transmitting frames, without updating the send indices, on the host is
equal to or has exceeded the threshold set in the Send_Max_Coalesced_BD register (see
Coalesced BD Count Register (Offset: 0x3c14)" on page
(not frames) meets the thresholds set in the various coalescing registers (see
Processing," on page 229
• The receive coalescing timer has expired, and new frames have been received on any of the receive rings,
and a host update has not occurred. The receive coalescing timer is then reset to the value in the
Receive_Coalescing_Ticks register (see
• The send coalescing timer has expired, and new frames have been consumed from any send ring, and a
host update has not occurred. The send coalescing timer is then reset to the value in the
Send_Coalescing_Ticks register.

MSI FIFO

This FIFO is eight entries deep and four bits wide. This FIFO is used to send MSIs via the PCI interface. The
host coalescing engine uses this FIFO to enqueue requests for the generation of MSI. There are no configurable
options for this FIFO and this FIFOs operation is completely transparent to host software.

Status Block

This data structure contains consumer and producer indices/values. Host software reads this control block, to
assess hardware updates in the send and receive rings. Two copies of the status block exist. The local copy is
DMAed to host memory by the DMA write engine. Host software does not want to generate PCI transactions to
read ring status; rather quicker memory bus transactions are desired. The host coalescing engine enqueues a
request to the DMA write engine, so host software gets a refreshed copy of status. The status block is refreshed
before a line IRQ or MSI is generated. See
status block.
Broadcom
®
January 29, 2016 • 5718-PG108-R
for more information).
"Send Coalescing Ticks Register (Offset: 0x3c0c)" on page
"Status Block Format" on page 82
254).
254). Updates can occur when the number of BDs
Section 11: "Interrupt
for a complete discussion of the
Host Coalescing
"Receive Max
"Send Max
254).
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