Ac Electrical Specifications - Imp Bus Master Cycles - Motorola MC68302 User Manual

6.8 AC ELECTRICAL SPECIFICATIONS - IMP BUS MASTER CYCLES
(Continued)
Num.
16 MHz
Characteristic Symbol Unit
Min Max
46 BGACK Width Low
!GAL
1.5
-
elks
47 Asynchronous Input Setup Time lsee Note 5)
lASI
10
-
ns
48
BEAR Asserted to DTACK Asserted (see Notes 2 and 3)
tBELDAL
10
-
ns
53 Data-Out Hold from Clock High
tcHDOI
0
-
ns
55 R/W Asserted to Data Bus Impedance Change
tRLDBD
0
-
ns
56 HALT/RESET Pulse Width I see Note 4)
lHRPW
10
-
elks
57
BGACK Negated to AS, DS, RiW Driven
tGASD
1.5
-
elks
57A
BGACK Negated to FC
lGAFD
1
-
elks
58 BR Negated to AS, DS, R/W Driven lsee Note 7)
lRHSD
1.5
-
elks
58A BR Negated to FC lsee Note 7)
lRHFD
1
-
elks
60 Clock High to BCLR Asserted
lCHBCL
-
30 ns
61 Clock High to BCLR Negated
tCHBCH
-
30 ns
62 Clock Low ISO Falling Edge) to RMC Asserted
tcLRML
-
30
ns
63 Clock High IS7 Rising Edge) to RMC Asserted
tcHRMH
-
30 ns
64 RMC Negated to BG Asserted (see Note 9)
tRMHGL
-
30 ns
NOTES:
1. For loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the
maximum columns.
2. Actual value depends on clock period.
3. If #47 is satisfied for both DTACK and BEAR, #48 may be ignored. In the absence of DTACK, BEAR is a synchronous
input using the asynchronous input setup time (#47).
4. For powerup, the MC68302 must be held in the reset state for 100 milliseconds to allow stabilization of on-chip circuit.
After the system is powered up #56 refers to the minimum pulse width required to reset the processor.
5. If the asynchronous input setup (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time 1#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time 1#27) for the following clock
cycle.
6. When AS and RiW are equally loaded ( ± 20%), subtract 5 nanoseconds from the values given in these columns.
7. The MC68302 will negate BG and begin driving the bus if external arbitration logic negates BG before
assert~
BGACK.
8. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be
reasserted.
9. This specification is valid only when the RMCST bit is set in the SCR register.
6-6
MC68302 USER'S MANUAL
MOTOROLA