Recommended Start-Up Sequence - Analog Devices AD9739 Manual

AD9739

RECOMMENDED START-UP SEQUENCE

The steps necessary to optimize the performance of the part and generate an output waveform are as follows:
1. Enable clocks to the controller and set the full-scale current. The registers and bits used in this step are shown in Table 35.
Recommended values for the bits are in parentheses.
Table 35.
Register Address 1 Bit 7
CNT_CLK 0x02 02 N/A
_Dis
FSC_1 0x06 06 FSC[7] (0)
FSC_2 0x07 07 Sleep (0)
1 The two-digit number is the decimal representation of the address.
2. Select the decoder mode. Recommended values for the bits are in parenthesis in Table 36, Table 37, and Table 38.
Table 36. Normal Mode
Register Address 1 Bit 7
Decoder_ 0x08 08 N/A
CNT
1 The two-digit number is the decimal representation of the address.
Table 37. RZ Mode
1
Register Address Bit 7
Decoder_ 0x08 08 N/A
CNT
1 The two-digit number is the decimal representation of the address.
Table 38. Mix Mode
1
Register Address Bit 7
Decoder_ 0x08 08 N/A
CNT
1
The two-digit number is the decimal representation of the address.
3. Set the cross control to the optimal setting. Recommended values for the bits are in parenthesis in Table 39.
Table 39.
1
Register Address
CROS_CNT1 0x22 34
CROS_CNT2 0x23 35
1
The two-digit number is the decimal representation of the address.
4. Enable the mu controller and ensure that it locks. Recommended values for the bits are in parenthesis in Table 40. To optimize and
lock the mu controller, it is only necessary to have the DAC clock running; no data need be presented to the DAC to optimize this
controller. It is recommended to write to Register 0x26 last, after all other mu controller registers in the table are written to, to ensure
that the controller is set up correctly before it is enabled.
Bit 6 Bit 5
N/A N/A
FSC[6] FSC[5]
(0) (0)
N/A N/A
Bit 6 Bit 5 Bit 4
N/A N/A N/A
Bit 6 Bit 5 Bit 4
N/A N/A N/A
Bit 6 Bit 5 Bit 4
N/A N/A N/A
Bit 7 Bit 6 Bit 5 Bit 4
N/A N/A N/A DIR_P (0)
N/A N/A N/A DIR_N (0)
Bit 4 Bit 3 Bit 2
N/A CLKGEN_PD N/A
(0)
FSC[4] FSC[3] (0) FSC[2]
(0) (0)
N/A N/A N/A
Bit 3 Bit 2 Bit 1
N/A N/A DAC_DEC[1] (0)
Bit 3 Bit 2 Bit 1
N/A N/A DAC_DEC[1] (0)
Bit 3 Bit 2 Bit 1
N/A N/A DAC_DEC[1] (1)
Bit 3 Bit 2
CLKP_OFFSET CLKP_
[3] (1) OFFSET
[2] (1)
CLKN_OFFSET CLKN_
[3] (1) OFFSET
[2] (1)
Rev. A | Page 50 of 56
Recommended
Bit 1 Bit 0 Value
REC_CNT_ MU_CNT_ 0x03
CLK (1) CLK (1)
FSC[1] (0) FSC[0] (0) 0x00
FSC[9] (1) FSC[8] (0) 0x02
Recommended
Bit 0 Value
DAC_DEC[0] (0) 0x00
Recommended
Bit 0 Value
DAC_DEC[0] (1) 0x01
Recommended
Bit 0 Value
DAC_DEC[0] (0) 0x02
Recommended
Bit 1 Bit 0 Value
CLKP_ CLKP_ 0x0F
OFFSET[1] OFFSET[
(1) 0] (1)
CLKN_ CLKN_ 0x0F
OFFSET[1] OFFSET
(1) [0] (1)