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6.10
BIT SEQUENTIAL BUFFER ..... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.
Address bit
FC3H
3
2
Symbol
BSB3
L register
L = F
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
7.
INTERRUPT FUNCTIONS
The µ PD75512 has 7 different interrupt sources and multiplexed interrupt with priority order.
In addition to that, the µ PD75512 is also provided with two types of test sources, of which INT2 has two types
of edge detection testable inputs.
The interrupt control circuit of the µ PD75512 has these functions:
• Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by
using the interrupt flag (IExxx) and interrupt master enable flag (IME).
• The interrupt start address can be arbitrarily set.
• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of
software).
• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
FC2H
1
0
3
2
1
BSB2
L = C L = B
INCS L
Fig. 6-11 Bit Sequential Buffer Format
FC1H
0
3
2
1
0
BSB1
L = 8 L = 7
L = 4 L = 3
DECS L
µ PD75512
FC0H
3
2
1
0
BSB0
L = 0
31
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