Figure 13-38: Repeat Transfer (Transmission/Reception) Timing Chart - NEC V850E/CA2 JUPITER Preliminary User's Manual

Figure 13-38: Repeat Transfer (Transmission/Reception) Timing Chart

SCK0n (input/output)
SO0n (output)
SI0n (input)
SOTBFLn
register
SOTBLn
register
SIOLn
register
SIRBLn
register
SOTBFn (d1)
Reg_WR
Reg_RD
CSOT bit
INTCSIn
interrupt
rq_clr
trans_rq
<1>
<2>
Remarks: 1. n = 0 to 2
2. Reg_WR:Internal signal. This signal indicates that the transmit data buffer register
(SOTBn/SOTBLn) has been written.
Reg_RD:Internal signal. This signal indicates that the receive data buffer register
(SIRBn/SIRBLn) has been read.
rq_clr: Internal signal. Transfer request clear signal.
trans_rq: Internal signal. Transfer request signal.
In the case of the repeat transfer mode, two transfer requests are set at the start of the first
transfer. Following the transmission/reception completion interrupt request (INTCSI0n), transfer is
continued if the SOTBn register can be written within the next transfer reservation period. If the
SOTBn register cannot be written, transfer ends and the SIRBn register does not receive the new
value of the SIOn register. The last receive data can be obtained by reading the SIOn register
following completion of the transfer.
Chapter 13 Serial Interface Function
dout-1 dout-2
din-1 din-2
dout-1
dout-2
din-1
SOTBn (d2) SOTBn (d3)
<3> <4> <5>
Period during which
next transfer can be
reserved
Preliminary User's Manual U15839EE1V0UM00
dout-3
din-3
dout-3 dout-4
din-2 din-3
SOTBn (d4)
SIRBn (d1) SIRBn (d2)
<4> <5> <4>
<6>
dout-4 dout-5
din-4 din-5
dout-5
din-4
SOTBn (d5)
SIRBn (d3) SIRBn (d4)
<5> < 7>
din-5
SIOn (d5)
<8>
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